Add Int32x4 Wasm Simd Binops, compare ops, select

Add Int32x4 Wasm Simd Binops, compare ops, select
 - Added: Int32x4Mul, Int32x4Min, Int32x4Max, Int32x4Equal, Int32x4NotEqual
 Uint32x4Min, Uint32x4Max
 - Fix I32x4Splat

R=bbudge@chromium.org, bradnelson@chromium.org, mtrofin@chromium.org

Review-Url: https://codereview.chromium.org/2719953002
Cr-Commit-Position: refs/heads/master@{#43827}
Committed: https://chromium.googlesource.com/v8/v8/+/16796914cb2745bfa90e76fdb280bcf97589610c

[gdeepti, 2017-02-27 13:58:27]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-27 13:58:31]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[gdeepti, 2017-02-27 14:14:44]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-27 14:14:53]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-02-27 14:39:35]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-02-27 14:39:36]

Dry run: This issue passed the CQ dry run.

[gdeepti, 2017-02-27 19:03:32]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-27 19:03:35]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[bbudge, 2017-02-27 19:15:03]

https://codereview.chromium.org/2719953002/diff/60001/src/compiler/x64/code-g...
File src/compiler/x64/code-generator-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/60001/src/compiler/x64/code-g...
src/compiler/x64/code-generator-x64.cc:2160: __ Pshufd(dst, dst, 0x0);
This will use AVX if it's available. Are we concerned that we would then be
mixing AVX and SSE instructions (hard coded below)? Is V8 using the VEX prefix
for SSE instructions when AVX is available?

[commit-bot: I haz the power, 2017-02-27 19:24:45]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-02-27 19:24:46]

Dry run: This issue passed the CQ dry run.

[gdeepti, 2017-02-28 03:36:17]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-28 03:36:23]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[gdeepti, 2017-02-28 03:36:42]

https://codereview.chromium.org/2719953002/diff/60001/src/compiler/x64/code-g...
File src/compiler/x64/code-generator-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/60001/src/compiler/x64/code-g...
src/compiler/x64/code-generator-x64.cc:2160: __ Pshufd(dst, dst, 0x0);
On 2017/02/27 19:15:03, bbudge wrote:
> This will use AVX if it's available. Are we concerned that we would then be
> mixing AVX and SSE instructions (hard coded below)? Is V8 using the VEX prefix
> for SSE instructions when AVX is available?

This will use AVX when available, I noticed that most packed integer
instructions have the AVX version implemented as well, so added this. Removed
now till we have support for all the AVX versions of simd instructions or
consistently use the instructions in the macro-assembler for the switch between
AVX/SSE.

[commit-bot: I haz the power, 2017-02-28 04:17:44]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-02-28 04:17:44]

Dry run: Try jobs failed on following builders:
  v8_linux64_gyp_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_gyp_rel_ng/build...)
  v8_linux64_gyp_rel_ng_triggered on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_gyp_rel_ng_trigg...)

[gdeepti, 2017-02-28 09:36:00]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-28 09:44:10]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-02-28 10:07:32]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-02-28 10:07:33]

Dry run: This issue passed the CQ dry run.

[gdeepti, 2017-02-28 11:07:03]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-02-28 11:07:11]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-02-28 11:31:39]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-02-28 11:31:40]

Dry run: This issue passed the CQ dry run.

[bbudge, 2017-02-28 19:34:39]

https://codereview.chromium.org/2719953002/diff/100001/src/compiler/x64/instr...
File src/compiler/x64/instruction-selector-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/100001/src/compiler/x64/instr...
src/compiler/x64/instruction-selector-x64.cc:2290: #define
VISIT_SIMD_BINOP(Opcode)                                            \
Nit: I think it's good to keep the ordering of ops consistent.

Types: Float32x4, Int32x4, Uint32x4, Int16x8, etc.

Ops: Splat, ExtractLane, ReplaceLane, Unops, Binops, etc.

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/code-...
File src/compiler/x64/code-generator-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/code-...
src/compiler/x64/code-generator-x64.cc:2159: __ Movd(dst, i.InputRegister(0));
Still might use AVX.

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/code-...
src/compiler/x64/code-generator-x64.cc:2234: XMMRegister dst =
i.OutputSimd128Register();
A comment here that dst contains the mask initially.

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/code-...
src/compiler/x64/code-generator-x64.cc:2235: __ xorps(i.InputSimd128Register(1),
i.InputSimd128Register(2));
Maybe use the scratch FP register for this? Otherwise, we overwrite the first
input.

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/instr...
File src/compiler/x64/instruction-selector-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/instr...
src/compiler/x64/instruction-selector-x64.cc:2295: #define
VISIT_SIMD_BINOP(Opcode)                                            \
nit: Elsewhere, we follow the general ordering:
Types: Float32x4, Int32x4, Uint32x4, Int16x8,...
Ops: Splat, ExtractLane, ReplaceLane, Unops, Binops, ...

https://codereview.chromium.org/2719953002/diff/140001/test/cctest/wasm/test-...
File test/cctest/wasm/test-run-wasm-simd.cc (right):

https://codereview.chromium.org/2719953002/diff/140001/test/cctest/wasm/test-...
test/cctest/wasm/test-run-wasm-simd.cc:909: // Test Select by making a mask
where the first two lanes are true and the rest
It would be better to adjust the #ifdefs rather than moving big blocks of code,
so we can have a somewhat consistent ordering of types and operations. You'll
get less blame that way too!

[gdeepti, 2017-03-13 19:55:34]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-03-13 19:55:42]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-03-13 20:13:22]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-03-13 20:13:23]

Dry run: Try jobs failed on following builders:
  v8_win_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_win_rel_ng/builds/24110)
  v8_win_rel_ng_triggered on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_win_rel_ng_triggered/bui...)

[gdeepti, 2017-03-13 20:33:13]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-03-13 20:33:19]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[gdeepti, 2017-03-13 20:37:52]

https://codereview.chromium.org/2719953002/diff/100001/src/compiler/x64/instr...
File src/compiler/x64/instruction-selector-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/100001/src/compiler/x64/instr...
src/compiler/x64/instruction-selector-x64.cc:2290: #define
VISIT_SIMD_BINOP(Opcode)                                            \
On 2017/02/28 19:34:39, bbudge wrote:
> Nit: I think it's good to keep the ordering of ops consistent.
> 
> Types: Float32x4, Int32x4, Uint32x4, Int16x8, etc.
> 
> Ops: Splat, ExtractLane, ReplaceLane, Unops, Binops, etc.

Done.

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/code-...
File src/compiler/x64/code-generator-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/code-...
src/compiler/x64/code-generator-x64.cc:2159: __ Movd(dst, i.InputRegister(0));
On 2017/02/28 19:34:39, bbudge wrote:
> Still might use AVX.

Fixed now.

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/code-...
src/compiler/x64/code-generator-x64.cc:2234: XMMRegister dst =
i.OutputSimd128Register();
On 2017/02/28 19:34:39, bbudge wrote:
> A comment here that dst contains the mask initially.

Done.

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/code-...
src/compiler/x64/code-generator-x64.cc:2235: __ xorps(i.InputSimd128Register(1),
i.InputSimd128Register(2));
On 2017/02/28 19:34:39, bbudge wrote:
> Maybe use the scratch FP register for this? Otherwise, we overwrite the first
> input.

Done.

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/instr...
File src/compiler/x64/instruction-selector-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/140001/src/compiler/x64/instr...
src/compiler/x64/instruction-selector-x64.cc:2295: #define
VISIT_SIMD_BINOP(Opcode)                                            \
On 2017/02/28 19:34:39, bbudge wrote:
> nit: Elsewhere, we follow the general ordering:
> Types: Float32x4, Int32x4, Uint32x4, Int16x8,...
> Ops: Splat, ExtractLane, ReplaceLane, Unops, Binops, ...

Done.

https://codereview.chromium.org/2719953002/diff/140001/test/cctest/wasm/test-...
File test/cctest/wasm/test-run-wasm-simd.cc (right):

https://codereview.chromium.org/2719953002/diff/140001/test/cctest/wasm/test-...
test/cctest/wasm/test-run-wasm-simd.cc:909: // Test Select by making a mask
where the first two lanes are true and the rest
On 2017/02/28 19:34:39, bbudge wrote:
> It would be better to adjust the #ifdefs rather than moving big blocks of
code,
> so we can have a somewhat consistent ordering of types and operations. You'll
> get less blame that way too!

Sgtm, makes a lot more sense to move the macros, fixed now!

[commit-bot: I haz the power, 2017-03-13 21:01:16]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-03-13 21:01:17]

Dry run: This issue passed the CQ dry run.

[bbudge, 2017-03-14 17:50:40]

Looking good, just a few comments.

https://codereview.chromium.org/2719953002/diff/180001/src/compiler/instructi...
File src/compiler/instruction-selector.cc (right):

https://codereview.chromium.org/2719953002/diff/180001/src/compiler/instructi...
src/compiler/instruction-selector.cc:2058: void
InstructionSelector::VisitInt32x4NotEqual(Node* node) { UNIMPLEMENTED(); }
nit: relational ops after binops.

https://codereview.chromium.org/2719953002/diff/180001/src/compiler/instructi...
src/compiler/instruction-selector.cc:2082: void
InstructionSelector::VisitSimd32x4Select(Node* node) { UNIMPLEMENTED(); }
nit: keep non-numeric ops together, i.e. with other Select ops.

It would be good for us to have a convention about SIMD operation ordering. 
There's a large renaming coming (to a single op naming convention, following the
one in wasm-opcodes.h) and that is probably the ordering we should follow.

https://codereview.chromium.org/2719953002/diff/180001/src/compiler/x64/code-...
File src/compiler/x64/code-generator-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/180001/src/compiler/x64/code-...
src/compiler/x64/code-generator-x64.cc:2175: CpuFeatureScope sse_scope(masm(),
SSE4_1);
Do all x64 chips support SSE4.1? This makes me wonder:

http://stackoverflow.com/questions/28185844/do-all-64-bit-intel-architectures...

If not, we should gate IsSimdSupported on this feature, i.e. don't always return
true.

[gdeepti, 2017-03-14 21:05:57]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-03-14 21:06:04]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-03-14 21:07:33]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-03-14 21:07:34]

Dry run: Try jobs failed on following builders:
  v8_android_arm_compile_rel on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_android_arm_compile_rel/...)
  v8_linux64_asan_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_asan_rel_ng/buil...)
  v8_linux64_gyp_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_gyp_rel_ng/build...)
  v8_linux64_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_rel_ng/builds/22519)
  v8_linux64_verify_csa_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux64_verify_csa_rel_n...)
  v8_linux_arm_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_arm_rel_ng/builds/...)
  v8_linux_gcc_compile_rel on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_gcc_compile_rel/bu...)
  v8_linux_mipsel_compile_rel on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_linux_mipsel_compile_rel...)
  v8_mac_rel_ng on master.tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_mac_rel_ng/builds/19000)

[gdeepti, 2017-03-14 21:26:12]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-03-14 21:26:25]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[gdeepti, 2017-03-14 21:32:52]

https://codereview.chromium.org/2719953002/diff/180001/src/compiler/instructi...
File src/compiler/instruction-selector.cc (right):

https://codereview.chromium.org/2719953002/diff/180001/src/compiler/instructi...
src/compiler/instruction-selector.cc:2058: void
InstructionSelector::VisitInt32x4NotEqual(Node* node) { UNIMPLEMENTED(); }
On 2017/03/14 17:50:39, bbudge wrote:
> nit: relational ops after binops.

Done.

https://codereview.chromium.org/2719953002/diff/180001/src/compiler/instructi...
src/compiler/instruction-selector.cc:2082: void
InstructionSelector::VisitSimd32x4Select(Node* node) { UNIMPLEMENTED(); }
On 2017/03/14 17:50:39, bbudge wrote:
> nit: keep non-numeric ops together, i.e. with other Select ops.
> 
> It would be good for us to have a convention about SIMD operation ordering. 
> There's a large renaming coming (to a single op naming convention, following
the
> one in wasm-opcodes.h) and that is probably the ordering we should follow.

Moved Select back, and changed ifdefs. 

Done.

https://codereview.chromium.org/2719953002/diff/180001/src/compiler/x64/code-...
File src/compiler/x64/code-generator-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/180001/src/compiler/x64/code-...
src/compiler/x64/code-generator-x64.cc:2175: CpuFeatureScope sse_scope(masm(),
SSE4_1);
On 2017/03/14 17:50:39, bbudge wrote:
> Do all x64 chips support SSE4.1? This makes me wonder:
> 
>
http://stackoverflow.com/questions/28185844/do-all-64-bit-intel-architectures...
> 
> If not, we should gate IsSimdSupported on this feature, i.e. don't always
return
> true.

Summarizing offline discussions, As SupportsSimd128() is vague, changed to
SupportsWasmSimd128(), on x64 and ia32 gated on SSE4_1 support and NEON support
on Arm.

https://codereview.chromium.org/2719953002/diff/220001/src/arm/assembler-arm-...
File src/arm/assembler-arm-inl.h (right):

https://codereview.chromium.org/2719953002/diff/220001/src/arm/assembler-arm-...
src/arm/assembler-arm-inl.h:51: bool CpuFeatures::SupportsWasmSimd128() { return
IsSupported(NEON); }
Bill, is this the right granularity for Arm?

[gdeepti, 2017-03-14 21:43:26]

The CQ bit was checked by gdeepti@chromium.org to run a CQ dry run

[commit-bot: I haz the power, 2017-03-14 21:43:35]

Dry run: CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-03-14 22:08:01]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2017-03-14 22:08:02]

Dry run: This issue passed the CQ dry run.

[bbudge, 2017-03-14 22:19:28]

bbudge@chromium.org changed reviewers:
+ jing.bao@intel.com

[bbudge, 2017-03-14 22:19:29]

LGTM thanks for fixing the capabilities testing.

+Jing for ia32.

https://codereview.chromium.org/2719953002/diff/260001/src/ia32/assembler-ia3...
File src/ia32/assembler-ia32-inl.h (right):

https://codereview.chromium.org/2719953002/diff/260001/src/ia32/assembler-ia3...
src/ia32/assembler-ia32-inl.h:51: bool CpuFeatures::SupportsWasmSimd128() {
return IsSupported(SSE4_1); }
I think this could be weaker with the current code: IsSupported(SSE3).

cc'ing Jing to verify.

[gdeepti, 2017-03-14 22:26:09]

https://codereview.chromium.org/2719953002/diff/260001/src/ia32/assembler-ia3...
File src/ia32/assembler-ia32-inl.h (right):

https://codereview.chromium.org/2719953002/diff/260001/src/ia32/assembler-ia3...
src/ia32/assembler-ia32-inl.h:51: bool CpuFeatures::SupportsWasmSimd128() {
return IsSupported(SSE4_1); }
On 2017/03/14 22:19:29, bbudge wrote:
> I think this could be weaker with the current code: IsSupported(SSE3).
> 
> cc'ing Jing to verify.

Defer to Jing here, but added this with the assumption that to support a
complete set of opcodes as in the current Wasm spec, SSE4.1 support will be
required.

[gdeepti, 2017-03-14 22:43:04]

gdeepti@chromium.org changed reviewers:
+ bmeurer@chromium.org

[gdeepti, 2017-03-14 22:43:05]

Adding bmeurer@ for owners review in src/compiler/ as mtrofin@ is on vacation.

[Benedikt Meurer, 2017-03-15 04:40:46]

LGTM on compiler.

[Jing, 2017-03-15 08:20:33]

https://codereview.chromium.org/2719953002/diff/260001/src/compiler/x64/code-...
File src/compiler/x64/code-generator-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/260001/src/compiler/x64/code-...
src/compiler/x64/code-generator-x64.cc:2227: __ xorps(dst,
i.InputSimd128Register(2));
Just for your information that blendvps in SSE4_1 can also do this work with one
single instruction. But if AVX isn't supported, it requires the mask to be in
xmm0.

https://codereview.chromium.org/2719953002/diff/260001/src/ia32/assembler-ia3...
File src/ia32/assembler-ia32-inl.h (right):

https://codereview.chromium.org/2719953002/diff/260001/src/ia32/assembler-ia3...
src/ia32/assembler-ia32-inl.h:51: bool CpuFeatures::SupportsWasmSimd128() {
return IsSupported(SSE4_1); }
On 2017/03/14 22:26:09, gdeepti wrote:
> On 2017/03/14 22:19:29, bbudge wrote:
> > I think this could be weaker with the current code: IsSupported(SSE3).
> > 
> > cc'ing Jing to verify.
> 
> Defer to Jing here, but added this with the assumption that to support a
> complete set of opcodes as in the current Wasm spec, SSE4.1 support will be
> required. 

I think the strict check for SSE4_1 is needed, because some WASM SIMD opcodes
will use SSE4_1 instructions. Otherwise we have to emulate all of them with
SSE/SSE2 in order to support older platforms.

[gdeepti, 2017-03-15 13:23:03]

https://codereview.chromium.org/2719953002/diff/260001/src/compiler/x64/code-...
File src/compiler/x64/code-generator-x64.cc (right):

https://codereview.chromium.org/2719953002/diff/260001/src/compiler/x64/code-...
src/compiler/x64/code-generator-x64.cc:2227: __ xorps(dst,
i.InputSimd128Register(2));
On 2017/03/15 08:20:33, Jing wrote:
> Just for your information that blendvps in SSE4_1 can also do this work with
one
> single instruction. But if AVX isn't supported, it requires the mask to be in
> xmm0.

Thanks for the pointer, as I understand it this is probably a better
implementation of Select as blendvps has hard constraints on the mask to be
specified in XMM0 and values into xmm1. Agree that it is better for the AVX
version of Select to use blendvps.

https://codereview.chromium.org/2719953002/diff/260001/src/ia32/assembler-ia3...
File src/ia32/assembler-ia32-inl.h (right):

https://codereview.chromium.org/2719953002/diff/260001/src/ia32/assembler-ia3...
src/ia32/assembler-ia32-inl.h:51: bool CpuFeatures::SupportsWasmSimd128() {
return IsSupported(SSE4_1); }
On 2017/03/15 08:20:33, Jing wrote:
> On 2017/03/14 22:26:09, gdeepti wrote:
> > On 2017/03/14 22:19:29, bbudge wrote:
> > > I think this could be weaker with the current code: IsSupported(SSE3).
> > > 
> > > cc'ing Jing to verify.
> > 
> > Defer to Jing here, but added this with the assumption that to support a
> > complete set of opcodes as in the current Wasm spec, SSE4.1 support will be
> > required. 
> 
> I think the strict check for SSE4_1 is needed, because some WASM SIMD opcodes
> will use SSE4_1 instructions. Otherwise we have to emulate all of them with
> SSE/SSE2 in order to support older platforms.

Thanks for confirming, will leave this as a check for SSE4_1

[gdeepti, 2017-03-15 13:23:12]

The CQ bit was checked by gdeepti@chromium.org

[commit-bot: I haz the power, 2017-03-15 13:23:15]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2017-03-15 13:24:55]

CQ is committing da patch.

Bot data: {"patchset_id": 260001, "attempt_start_ts": 1489584192527130,
"parent_rev": "387e2aca5e4da925f5d156315485ec27bb88c685", "commit_rev":
"16796914cb2745bfa90e76fdb280bcf97589610c"}

[commit-bot: I haz the power, 2017-03-15 13:25:01]

Description was changed from

==========
Add Int32x4 Wasm Simd Binops, compare ops, select
 - Added: Int32x4Mul, Int32x4Min, Int32x4Max, Int32x4Equal, Int32x4NotEqual
 Uint32x4Min, Uint32x4Max
 - Fix I32x4Splat

R=bbudge@chromium.org, bradnelson@chromium.org, mtrofin@chromium.org
==========

to

==========
Add Int32x4 Wasm Simd Binops, compare ops, select
 - Added: Int32x4Mul, Int32x4Min, Int32x4Max, Int32x4Equal, Int32x4NotEqual
 Uint32x4Min, Uint32x4Max
 - Fix I32x4Splat

R=bbudge@chromium.org, bradnelson@chromium.org, mtrofin@chromium.org

Review-Url: https://codereview.chromium.org/2719953002
Cr-Commit-Position: refs/heads/master@{#43827}
Committed:
https://chromium.googlesource.com/v8/v8/+/16796914cb2745bfa90e76fdb280bcf9758...
==========

[commit-bot: I haz the power, 2017-03-15 13:25:02]

Committed patchset #14 (id:260001) as
https://chromium.googlesource.com/v8/v8/+/16796914cb2745bfa90e76fdb280bcf9758...