Index: src/ia32/assembler-ia32.h |
diff --git a/src/ia32/assembler-ia32.h b/src/ia32/assembler-ia32.h |
index 76bceb64c87846f9a234859fd1649d84445ff46e..a4bc98d11435a5200e356d3524c1d00d6ade9276 100644 |
--- a/src/ia32/assembler-ia32.h |
+++ b/src/ia32/assembler-ia32.h |
@@ -40,7 +40,6 @@ |
#include <deque> |
#include "src/assembler.h" |
-#include "src/ia32/sse-instr.h" |
#include "src/isolate.h" |
#include "src/utils.h" |
@@ -1419,30 +1418,6 @@ |
void vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); |
void vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); |
-// Other SSE and AVX instructions |
-#define DECLARE_SSE2_INSTRUCTION(instruction, prefix, escape, opcode) \ |
- void instruction(XMMRegister dst, XMMRegister src) { \ |
- instruction(dst, Operand(src)); \ |
- } \ |
- void instruction(XMMRegister dst, const Operand& src) { \ |
- sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \ |
- } |
- |
- SSE2_INSTRUCTION_LIST(DECLARE_SSE2_INSTRUCTION) |
-#undef DECLARE_SSE2_INSTRUCTION |
- |
-#define DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \ |
- void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \ |
- v##instruction(dst, src1, Operand(src2)); \ |
- } \ |
- void v##instruction(XMMRegister dst, XMMRegister src1, \ |
- const Operand& src2) { \ |
- vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \ |
- } |
- |
- SSE2_INSTRUCTION_LIST(DECLARE_SSE2_AVX_INSTRUCTION) |
-#undef DECLARE_SSE2_AVX_INSTRUCTION |
- |
// Prefetch src position into cache level. |
// Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a |
// non-temporal |
@@ -1573,10 +1548,6 @@ |
inline void emit_disp(Label* L, Displacement::Type type); |
inline void emit_near_disp(Label* L); |
- void sse2_instr(XMMRegister dst, const Operand& src, byte prefix, byte escape, |
- byte opcode); |
- void vinstr(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2, |
- SIMDPrefix pp, LeadingOpcode m, VexW w); |
// Most BMI instructions are similiar. |
void bmi1(byte op, Register reg, Register vreg, const Operand& rm); |
void bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg, |