Index: runtime/vm/simulator_arm64.h |
diff --git a/runtime/vm/simulator_arm64.h b/runtime/vm/simulator_arm64.h |
index 406976aaeecf32d2b681d37d85478763bb0f279f..79f9ced09ebe2f996ad8cd94b2ea7eabea45d811 100644 |
--- a/runtime/vm/simulator_arm64.h |
+++ b/runtime/vm/simulator_arm64.h |
@@ -50,8 +50,10 @@ class Simulator { |
// specifying the type. We also can't translate a dummy value for SPREG into |
// a real value because the architecture independent code expects SPREG to |
// be a real register value. |
- void set_register( |
- Instr* instr, Register reg, int64_t value, R31Type r31t = R31IsSP); |
+ void set_register(Instr* instr, |
+ Register reg, |
+ int64_t value, |
+ R31Type r31t = R31IsSP); |
int64_t get_register(Register reg, R31Type r31t = R31IsSP) const; |
void set_wregister(Register reg, int32_t value, R31Type r31t = R31IsSP); |
int32_t get_wregister(Register reg, R31Type r31t = R31IsSP) const; |
@@ -65,9 +67,7 @@ class Simulator { |
void get_vregister(VRegister reg, simd_value_t* value) const; |
void set_vregister(VRegister reg, const simd_value_t& value); |
- int64_t get_sp() const { |
- return get_register(SPREG); |
- } |
+ int64_t get_sp() const { return get_register(SPREG); } |
int64_t get_pc() const; |
int64_t get_last_pc() const; |
@@ -165,9 +165,7 @@ class Simulator { |
int64_t break_instr_; |
// Illegal memory access support. |
- static bool IsIllegalAddress(uword addr) { |
- return addr < 64*1024; |
- } |
+ static bool IsIllegalAddress(uword addr) { return addr < 64 * 1024; } |
void HandleIllegalAccess(uword addr, Instr* instr); |
// Handles an unaligned memory access. |
@@ -232,8 +230,10 @@ class Simulator { |
void SetNZFlagsX(int64_t val); |
bool CarryFromX(int64_t alu_out, int64_t left, int64_t right, bool addition); |
- bool OverflowFromX( |
- int64_t alu_out, int64_t left, int64_t right, bool addition); |
+ bool OverflowFromX(int64_t alu_out, |
+ int64_t left, |
+ int64_t right, |
+ bool addition); |
void SetCFlag(bool val); |
void SetVFlag(bool val); |
@@ -256,10 +256,9 @@ class Simulator { |
// Decode instructions. |
void InstructionDecode(Instr* instr); |
- #define DECODE_OP(op) \ |
- void Decode##op(Instr* instr); |
+#define DECODE_OP(op) void Decode##op(Instr* instr); |
APPLY_OP_LIST(DECODE_OP) |
- #undef DECODE_OP |
+#undef DECODE_OP |
// Executes ARM64 instructions until the PC reaches kEndSimulatingPC. |
void Execute(); |
@@ -268,9 +267,7 @@ class Simulator { |
bool IsTracingExecution() const; |
// Longjmp support for exceptions. |
- SimulatorSetjmpBuffer* last_setjmp_buffer() { |
- return last_setjmp_buffer_; |
- } |
+ SimulatorSetjmpBuffer* last_setjmp_buffer() { return last_setjmp_buffer_; } |
void set_last_setjmp_buffer(SimulatorSetjmpBuffer* buffer) { |
last_setjmp_buffer_ = buffer; |
} |