Thumb2 Backend: Make arithmetic instructions set condition codes by default

src/arm/assembler-thumb32.cc

Index: src/arm/assembler-thumb32.cc
diff --git a/src/arm/assembler-thumb32.cc b/src/arm/assembler-thumb32.cc
index b92512f0190e79d2241fdccf6ed887052a4e846c..77e57a91136c9e9f24da6e838fae50d517698771 100644
--- a/src/arm/assembler-thumb32.cc
+++ b/src/arm/assembler-thumb32.cc
@@ -334,7 +334,8 @@ Instr Assembler::thumb32_3reg_lsl(Register rd,
               break;
     case LSR: lsr_thumb(ip, Operand(x.rm_, LSR, x.shift_imm_), LeaveCC, al);
               break;
-    case ASR: asr_thumb(ip, Operand(x.rm_, ASR, x.shift_imm_), LeaveCC, al);
+    case ASR: asr_thumb(ip, Operand(x.rm_, ASR, x.shift_imm_),
+                        LeaveCC, al, false);
               break;
     default:  return (x.rn_.code()*BH0 | rd.code()*B12 | x.rm_.code());
   }
@@ -467,14 +468,14 @@ void Assembler::mov_reg_t3(Register dst, const Operand& src, SBit s,
 // teq imm t1 - mode 1
 void Assembler::teq_imm_t1(Register src1, Condition cond,
                            uint32_t i, uint32_t imm3, uint32_t imm8) {
-  emit32(thumb32_mode1(TEQ_32_IMM, SetCC) |
+  emit32(thumb32_mode1(TEQ_32_IMM, SetCCBit) |
          thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8) );
 }
 
 
 // teq reg t1 - mode 11
 void Assembler::teq_reg_t1(Register src1, const Operand& src2, Condition cond) {
-  emit32(thumb32_mode11(TEQ_32_REG, SetCC) |
+  emit32(thumb32_mode11(TEQ_32_REG, SetCCBit) |
          thumb32_3reg_shift_imm8(src1, pc, src2));
 }
 
@@ -483,7 +484,7 @@ void Assembler::teq_reg_t1(Register src1, const Operand& src2, Condition cond) {
 void Assembler::cmp_imm_t2(Register src1, Condition cond,
                            uint32_t i, uint32_t imm3, uint32_t imm8) {
   ASSERT(cond == al);
-  emit32(thumb32_mode1(CMP_32_IMM, SetCC) |
+  emit32(thumb32_mode1(CMP_32_IMM, SetCCBit) |
          thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8) );
 }
 
@@ -491,7 +492,7 @@ void Assembler::cmp_imm_t2(Register src1, Condition cond,
 // cmp reg t3 - mode 11
 void Assembler::cmp_reg_t3(Register src1, const Operand& src2, Condition cond) {
   ASSERT(cond == al);
-  emit32(thumb32_mode11(CMP_32_REG3, SetCC) |
+  emit32(thumb32_mode11(CMP_32_REG3, SetCCBit) |
          thumb32_3reg_shift_imm8(src1, pc, src2));
 }
 
@@ -689,7 +690,7 @@ void Assembler::rsb_reg_t1(Register dst, Register src1, const Operand& src2,
 void Assembler::tst_imm_t1(Register src1, Condition cond,
                            uint32_t i, uint32_t imm3, uint32_t imm8) {
 // Rn imm3 imm8 // 1reg
-  emit32(thumb32_mode1(TST_32_IMM, SetCC) |
+  emit32(thumb32_mode1(TST_32_IMM, SetCCBit) |
          thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8));
 }
 
@@ -698,7 +699,7 @@ void Assembler::tst_imm_t1(Register src1, Condition cond,
 void Assembler::tst_reg_t2(Register src1, const Operand& src2, Condition cond) {
 // Rn imm3 imm2 type Rm
   ASSERT(cond == al);
-  emit32(thumb32_mode11(TST_32_REG2, SetCC) |
+  emit32(thumb32_mode11(TST_32_REG2, SetCCBit) |
          thumb32_3reg_shift_imm8(src1, pc, src2));
 }
 
@@ -708,7 +709,7 @@ void Assembler::cmn_imm_t1(Register src1, Condition cond,
                            uint32_t i, uint32_t imm3, uint32_t imm8) {
   ASSERT(cond == al);
   // SetCC turns on BH4, which is on for cmm immediate T1
-  emit32(thumb32_mode1(CMN_32_IMM, SetCC) |
+  emit32(thumb32_mode1(CMN_32_IMM, SetCCBit) |
          thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8));
 }
 
@@ -718,7 +719,7 @@ void Assembler::cmn_reg_t2(Register src1, const Operand& src2, Condition cond) {
 // Rn imm3 imm2 type Rm // 2reg
   ASSERT(cond == al);
   // SetCC turns on BH4, which is on for cmm register T2
-  emit32(thumb32_mode11(CMN_32_REG2, SetCC) |
+  emit32(thumb32_mode11(CMN_32_REG2, SetCCBit) |
          thumb32_3reg_shift_imm8(src1, pc, src2));
 }