Thumb2 Backend: Make arithmetic instructions set condition codes by default

src/arm/assembler-thumb32.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 316 matching lines @@
   uint8_t imm2 = 0;
   if (x.shift_op_ == LSL && is_uint2(x.shift_imm_)) {
     imm2 = x.shift_imm_ & 3;
     return (x.rn_.code()*BH0 | rd.code()*B12 | imm2*B4 | x.rm_.code());
   }
   switch (x.shift_op_) {
     case LSL: lsl_thumb(ip, Operand(x.rm_, LSL, x.shift_imm_), LeaveCC, al);
               break;
     case LSR: lsr_thumb(ip, Operand(x.rm_, LSR, x.shift_imm_), LeaveCC, al);
               break;
-    case ASR: asr_thumb(ip, Operand(x.rm_, ASR, x.shift_imm_), LeaveCC, al);
+    case ASR: asr_thumb(ip, Operand(x.rm_, ASR, x.shift_imm_),
+                        LeaveCC, al, false);
               break;
     default:  return (x.rn_.code()*BH0 | rd.code()*B12 | x.rm_.code());
   }
   return (x.rn_.code()*BH0 | rd.code()*B12 | ip.code());
 }
 
 
 Instr Assembler::thumb32_4reg(Register dst, Register src1, Register src2,
                               Register srcA) {
   return (src1.code()*BH0 | srcA.code()*B12 | dst.code()*B8 | src2.code());
@@ skipping 112 matching lines @@
                            Condition cond) {
   ASSERT(cond == al);
   emit32(thumb32_mode11(MOV_32_REG3, s) |
          thumb32_3reg_shift_imm8(pc, dst, src));
 }
 
 
 // teq imm t1 - mode 1
 void Assembler::teq_imm_t1(Register src1, Condition cond,
                            uint32_t i, uint32_t imm3, uint32_t imm8) {
-  emit32(thumb32_mode1(TEQ_32_IMM, SetCC) |
+  emit32(thumb32_mode1(TEQ_32_IMM, SetCCBit) |
          thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8) );
 }
 
 
 // teq reg t1 - mode 11
 void Assembler::teq_reg_t1(Register src1, const Operand& src2, Condition cond) {
-  emit32(thumb32_mode11(TEQ_32_REG, SetCC) |
+  emit32(thumb32_mode11(TEQ_32_REG, SetCCBit) |
          thumb32_3reg_shift_imm8(src1, pc, src2));
 }
 
 
 // cmp imm t2 - mode 1
 void Assembler::cmp_imm_t2(Register src1, Condition cond,
                            uint32_t i, uint32_t imm3, uint32_t imm8) {
   ASSERT(cond == al);
-  emit32(thumb32_mode1(CMP_32_IMM, SetCC) |
+  emit32(thumb32_mode1(CMP_32_IMM, SetCCBit) |
          thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8) );
 }
 
 
 // cmp reg t3 - mode 11
 void Assembler::cmp_reg_t3(Register src1, const Operand& src2, Condition cond) {
   ASSERT(cond == al);
-  emit32(thumb32_mode11(CMP_32_REG3, SetCC) |
+  emit32(thumb32_mode11(CMP_32_REG3, SetCCBit) |
          thumb32_3reg_shift_imm8(src1, pc, src2));
 }
 
 
 // lsl imm t2 - mode UNKNOWN
 void Assembler::lsl_imm_t2(Register dst, const Operand& src, SBit s,
                            Condition cond) {
   ASSERT(cond == al);
   ASSERT(is_uint5(src.shift_imm_));
   ASSERT(dst.code() != 13);
@@ skipping 177 matching lines @@
 // S Rn imm3 Rd imm2 type Rm // 3reg
   emit32(thumb32_mode11(RSB_32_REG, s) |
          thumb32_3reg_shift_imm8(src1, dst, src2));
 }
 
 
 // tst imm t1 - mode 1
 void Assembler::tst_imm_t1(Register src1, Condition cond,
                            uint32_t i, uint32_t imm3, uint32_t imm8) {
 // Rn imm3 imm8 // 1reg
-  emit32(thumb32_mode1(TST_32_IMM, SetCC) |
+  emit32(thumb32_mode1(TST_32_IMM, SetCCBit) |
          thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8));
 }
 
 
 // tst reg t2 - mode 11
 void Assembler::tst_reg_t2(Register src1, const Operand& src2, Condition cond) {
 // Rn imm3 imm2 type Rm
   ASSERT(cond == al);
-  emit32(thumb32_mode11(TST_32_REG2, SetCC) |
+  emit32(thumb32_mode11(TST_32_REG2, SetCCBit) |
          thumb32_3reg_shift_imm8(src1, pc, src2));
 }
 
 
 // cmn imm t1 - mode 1
 void Assembler::cmn_imm_t1(Register src1, Condition cond,
                            uint32_t i, uint32_t imm3, uint32_t imm8) {
   ASSERT(cond == al);
   // SetCC turns on BH4, which is on for cmm immediate T1
-  emit32(thumb32_mode1(CMN_32_IMM, SetCC) |
+  emit32(thumb32_mode1(CMN_32_IMM, SetCCBit) |
          thumb32_2reg_thumb_expand_imm(pc, src1, i, imm3, imm8));
 }
 
 
 // cmn reg t2 - mode 11
 void Assembler::cmn_reg_t2(Register src1, const Operand& src2, Condition cond) {
 // Rn imm3 imm2 type Rm // 2reg
   ASSERT(cond == al);
   // SetCC turns on BH4, which is on for cmm register T2
-  emit32(thumb32_mode11(CMN_32_REG2, SetCC) |
+  emit32(thumb32_mode11(CMN_32_REG2, SetCCBit) |
          thumb32_3reg_shift_imm8(src1, pc, src2));
 }
 
 
 // bic imm t1 - mode 1
 void Assembler::bic_imm_t1(Register dst, Register src1, SBit s, Condition cond,
                            uint32_t i, uint32_t imm3, uint32_t imm8) {
   ASSERT(cond == al);
   emit32(thumb32_mode1(BIC_32_IMM, s) |
          thumb32_2reg_thumb_expand_imm(dst, src1, i, imm3, imm8));
@@ skipping 76 matching lines @@
 void Assembler::strd_imm_t1(Register src1, Register src2,
                      const MemOperand& dst) {
     emit32(thumb32_mode6(STRD_32_IMM2, STRD_32_IMM2_OP2) |
            thumb32_3reg_zero_extend_imm8(src1, src2, dst));
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM