Index: src/arm/assembler-thumb.cc |
diff --git a/src/arm/assembler-thumb.cc b/src/arm/assembler-thumb.cc |
index 129ec8ed0993efb6d20bb5c2d903937a2709b2ba..b2211e3462275124d846a1ac7ab595407b6efbfa 100644 |
--- a/src/arm/assembler-thumb.cc |
+++ b/src/arm/assembler-thumb.cc |
@@ -36,26 +36,28 @@ namespace v8 { |
namespace internal { |
void Assembler::add_thumb(Register dst, Register src1, const Operand& src2, |
- SBit s, Condition cond) { |
- ASSERT(cond == al); |
+ SBitMode smode, Condition cond) { |
+ bool is_in_it_block = emit_it(cond); |
+ SBit s = sbit_from_mode(smode); |
if (!src2.rm_.is_valid()) { |
// Immediate. |
- if (s == LeaveCC) { |
- if (is_uint12(src2.imm32_)) { |
- add_imm_t4(dst, src1, src2, s, cond); |
- return; |
- } |
- } else { |
+ if (it_block_smode_check(is_in_it_block, smode)) { |
if (is_uint3(src2.imm32_) && are_low_reg(dst, src1)) { |
emit16(thumb16_mode1(ADD_IMM_1) | |
thumb16_2lowreg_imm3_encoding(dst, src1, src2)); |
return; |
- } else if (is_uint8(src2.imm32_) && dst.code() == src1.code()) { |
+ } else if (is_low_reg(dst) && |
+ dst.code() == src1.code() && |
+ is_uint8(src2.imm32_)) { |
emit16(thumb16_mode1(ADD_IMM_2) | |
thumb16_lowreg_imm8_encoding(dst, src2)); |
return; |
} |
} |
+ if (smode != SetCC && is_uint12(src2.imm32_)) { |
+ add_imm_t4(dst, src1, src2, s, cond); |
+ return; |
+ } |
uint32_t i, imm3, imm8; |
if (thumb_expand_imm(src2.imm32_, &i, &imm3, &imm8)) { |
add_imm_t3(dst, src1, s, cond, i, imm3, imm8); |
@@ -63,15 +65,17 @@ void Assembler::add_thumb(Register dst, Register src1, const Operand& src2, |
} |
// Immediate - too big for 1 thumb instruction |
mov_thumb(ip, src2, LeaveCC, al); |
- add_thumb(dst, src1, Operand(ip), s, al); |
+ add_thumb(dst, src1, Operand(ip), smode, al); |
return; |
} else if (src2.shift_imm_ == 0) { |
// Register. |
- if (s == SetCC && are_low_reg(dst, src1) && is_low_reg(src2.rm_)) { |
+ if (it_block_smode_check(is_in_it_block, smode) && |
+ are_low_reg(dst, src1) && |
+ is_low_reg(src2.rm_)) { |
emit16(thumb16_mode1(ADD_REG_1) | |
thumb16_3lowreg_encoding(dst, src1, src2)); |
return; |
- } else if (s == LeaveCC && dst.code() == src1.code()) { |
+ } else if (smode != SetCC && dst.code() == src1.code()) { |
emit16(thumb16_mode3(ADD_REG_2) | |
thumb16_2anyreg_encoding(dst, src2)); |
return; |
@@ -82,26 +86,28 @@ void Assembler::add_thumb(Register dst, Register src1, const Operand& src2, |
void Assembler::sub_thumb(Register dst, Register src1, const Operand& src2, |
- SBit s, Condition cond) { |
- emit_it(cond); |
+ SBitMode smode, Condition cond) { |
+ bool is_in_it_block = emit_it(cond); |
+ SBit s = sbit_from_mode(smode); |
if (!src2.rm_.is_valid()) { |
// Immediate. |
- if (s == LeaveCC) { |
- if (is_uint12(src2.imm32_)) { |
- sub_imm_t4(dst, src1, src2, s, cond); |
- return; |
- } |
- } else { |
+ if (it_block_smode_check(is_in_it_block, smode)) { |
if (is_uint3(src2.imm32_) && are_low_reg(dst, src1)) { |
emit16(thumb16_mode1(SUB_IMM_1) | |
thumb16_2lowreg_imm3_encoding(dst, src1, src2)); |
return; |
- } else if (is_uint8(src2.imm32_) && dst.code() == src1.code()) { |
+ } else if (is_low_reg(dst) && |
+ dst.code() == src1.code() && |
+ is_uint8(src2.imm32_)) { |
emit16(thumb16_mode1(SUB_IMM_2) | |
thumb16_lowreg_imm8_encoding(dst, src2)); |
return; |
} |
} |
+ if (smode != SetCC && is_uint12(src2.imm32_)) { |
+ sub_imm_t4(dst, src1, src2, s, cond); |
+ return; |
+ } |
uint32_t i, imm3, imm8; |
if (thumb_expand_imm(src2.imm32_, &i, &imm3, &imm8)) { |
sub_imm_t3(dst, src1, s, cond, i, imm3, imm8); |
@@ -109,11 +115,13 @@ void Assembler::sub_thumb(Register dst, Register src1, const Operand& src2, |
} |
ASSERT(cond == al); |
mov_thumb(ip, src2, LeaveCC, al); |
- sub_thumb(dst, src1, Operand(ip), s, al); |
+ sub_thumb(dst, src1, Operand(ip), smode, al); |
return; |
} else { |
// Register. |
- if (s == SetCC && are_low_reg(dst, src1) && is_low_reg(src2.rm_)) { |
+ if (it_block_smode_check(is_in_it_block, smode) && |
+ are_low_reg(dst, src1) && |
+ is_low_reg(src2.rm_)) { |
emit16(thumb16_mode1(SUB_REG) | |
thumb16_3lowreg_encoding(dst, src1, src2)); |
return; |
@@ -126,17 +134,20 @@ void Assembler::sub_thumb(Register dst, Register src1, const Operand& src2, |
} |
-void Assembler::mov_thumb(Register dst, const Operand& src, SBit s, |
+void Assembler::mov_thumb(Register dst, const Operand& src, SBitMode smode, |
Condition cond) { |
- emit_it(cond); |
+ bool is_in_it_block = emit_it(cond); |
+ SBit s = sbit_from_mode(smode); |
if (!src.rm_.is_valid()) { |
// Immediate. |
- if (is_uint8(src.imm32_) && is_low_reg(dst) && s == SetCC) { |
+ if (it_block_smode_check(is_in_it_block, smode) && |
+ is_uint8(src.imm32_) && |
+ is_low_reg(dst)) { |
emit16(thumb16_mode1(MOV_IMM) | |
thumb16_lowreg_imm8_encoding(dst, src)); |
return; |
} else { |
- if (is_uint16(src.imm32_) && s == LeaveCC) { |
+ if (is_uint16(src.imm32_) && smode != SetCC) { |
mov_imm_t3(dst, src, s, cond); |
return; |
} else { |
@@ -146,7 +157,7 @@ void Assembler::mov_thumb(Register dst, const Operand& src, SBit s, |
mov_imm_t2(dst, s, cond, i, imm3, imm8); |
return; |
} else { |
- move_32_bit_immediate_thumb(dst, s, src, cond); |
+ move_32_bit_immediate_thumb(dst, smode, src, cond); |
return; |
} |
} |
@@ -155,24 +166,25 @@ void Assembler::mov_thumb(Register dst, const Operand& src, SBit s, |
// Register. |
if (src.rs_.is_valid() || (!src.rs_.is_valid() && src.shift_imm_ != 0)) { |
switch (src.shift_op_) { |
- case LSL: lsl_thumb(dst, src, s, cond); |
+ case LSL: lsl_thumb(dst, src, smode, cond); |
return; |
- case LSR: lsr_thumb(dst, src, s, cond); |
+ case LSR: lsr_thumb(dst, src, smode, cond); |
return; |
- case ASR: asr_thumb(dst, src, s, cond); |
+ case ASR: asr_thumb(dst, src, smode, cond, is_in_it_block); |
return; |
- case ROR: ror_thumb(dst, src, s, cond); |
+ case ROR: ror_thumb(dst, src, smode, cond); |
return; |
case RRX: |
default: UNREACHABLE(); |
} |
return; |
} |
- if (s == LeaveCC) { |
+ if (smode != SetCC) { |
emit16(thumb16_mode3(MOV_REG_1) | |
thumb16_2anyreg_encoding(dst, src)); |
return; |
- } else if (are_low_reg(dst, src.rm_)) { |
+ } else if (smode != LeaveCC && !is_in_it_block && |
+ are_low_reg(dst, src.rm_)) { |
// Note: MOV_REG_2 is 0, so call not needed |
emit16(thumb16_2lowreg_encoding(dst, src)); |
return; |
@@ -252,11 +264,13 @@ void Assembler::cmp_thumb(Register dst, const Operand& src, Condition cond) { |
} |
-void Assembler::lsl_thumb(Register dst, const Operand& src, SBit s, |
+void Assembler::lsl_thumb(Register dst, const Operand& src, SBitMode smode, |
Condition cond) { |
ASSERT(cond == al); |
+ SBit s = sbit_from_mode(smode); |
if (!src.rs_.is_valid()) { |
- if (is_int5(src.shift_imm_) && are_low_reg(dst, src.rm_) && s == SetCC) { |
+ if (is_int5(src.shift_imm_) && are_low_reg(dst, src.rm_) && |
+ smode != LeaveCC) { |
emit16(thumb16_mode1(LSL_IMM) | |
thumb16_2lowreg_imm5_encoding(dst, src.rm_, src)); |
return; |
@@ -266,7 +280,7 @@ void Assembler::lsl_thumb(Register dst, const Operand& src, SBit s, |
} |
} else { |
// Register src{rm rs, shift_imm} |
- if (s == SetCC && dst.code() == src.rm_.code() && |
+ if (smode != LeaveCC && dst.code() == src.rm_.code() && |
are_low_reg(dst, src.rs_)) { |
// Register 16 |
emit16(thumb16_mode2(LSL_REG) | |
@@ -282,12 +296,14 @@ void Assembler::lsl_thumb(Register dst, const Operand& src, SBit s, |
} |
-void Assembler::lsr_thumb(Register dst, const Operand& src, SBit s, |
+void Assembler::lsr_thumb(Register dst, const Operand& src, SBitMode smode, |
Condition cond) { |
ASSERT(cond == al); |
+ SBit s = sbit_from_mode(smode); |
if (!src.rs_.is_valid()) { |
// Immediate |
- if (is_int5(src.shift_imm_) && are_low_reg(dst, src.rm_) && s == SetCC) { |
+ if (is_int5(src.shift_imm_) && are_low_reg(dst, src.rm_) && |
+ smode != LeaveCC) { |
// Immediate 16 |
emit16(thumb16_mode1(LSR_IMM) | |
thumb16_2lowreg_imm5_encoding(dst, src.rm_, src)); |
@@ -298,7 +314,7 @@ void Assembler::lsr_thumb(Register dst, const Operand& src, SBit s, |
return; |
} |
} else { |
- if (s == SetCC && dst.code() == src.rm_.code() && |
+ if (smode != LeaveCC && dst.code() == src.rm_.code() && |
are_low_reg(dst, src.rs_)) { |
emit16(thumb16_mode2(LSR_REG) | |
thumb16_2lowreg_encoding(dst, src.rs_)); |
@@ -312,12 +328,14 @@ void Assembler::lsr_thumb(Register dst, const Operand& src, SBit s, |
} |
-void Assembler::ror_thumb(Register dst, const Operand& src, SBit s, |
+void Assembler::ror_thumb(Register dst, const Operand& src, SBitMode smode, |
Condition cond) { |
ASSERT(cond == al); |
+ SBit s = sbit_from_mode(smode); |
if (!src.rs_.is_valid()) { |
// Immediate |
- if (is_int5(src.shift_imm_) && are_low_reg(dst, src.rm_) && s == SetCC) { |
+ if (is_int5(src.shift_imm_) && are_low_reg(dst, src.rm_) && |
+ smode != LeaveCC) { |
// Immediate 16 |
emit16(thumb16_mode1(ROR_IMM) | |
thumb16_2lowreg_imm5_encoding(dst, src.rm_, src)); |
@@ -328,7 +346,7 @@ void Assembler::ror_thumb(Register dst, const Operand& src, SBit s, |
return; |
} |
} else { |
- if (s == SetCC && dst.code() == src.rm_.code() && |
+ if (smode != LeaveCC && dst.code() == src.rm_.code() && |
are_low_reg(dst, src.rs_)) { |
emit16(thumb16_mode2(ROR_REG) | |
thumb16_2lowreg_encoding(dst, src.rs_)); |
@@ -342,11 +360,13 @@ void Assembler::ror_thumb(Register dst, const Operand& src, SBit s, |
} |
-void Assembler::asr_thumb(Register dst, const Operand& src, SBit s, |
- Condition cond) { |
+void Assembler::asr_thumb(Register dst, const Operand& src, SBitMode smode, |
+ Condition cond, bool is_in_it_block) { |
+ SBit s = sbit_from_mode(smode); |
if (!src.rs_.is_valid()) { |
// Immediate |
- if (is_int5(src.shift_imm_) && are_low_reg(dst, src.rm_) && s == SetCC) { |
+ if (is_int5(src.shift_imm_) && are_low_reg(dst, src.rm_) && |
+ it_block_smode_check(is_in_it_block, smode)) { |
// Immediate 16 |
emit16(thumb16_mode1(ASR_IMM) | |
thumb16_2lowreg_imm5_encoding(dst, src.rm_, src)); |
@@ -358,9 +378,9 @@ void Assembler::asr_thumb(Register dst, const Operand& src, SBit s, |
} |
} else { |
// Register |
- if (s == SetCC && dst.code() == src.rm_.code() && |
- are_low_reg(dst, src.rs_)) { |
- // Register 16 |
+ if (it_block_smode_check(is_in_it_block, smode) && |
+ dst.code() == src.rm_.code() && are_low_reg(dst, src.rs_)) { |
+ // Register 16 |
emit16(thumb16_mode2(ASR_REG) | |
thumb16_2lowreg_encoding(dst, src.rs_)); |
return; |
@@ -374,8 +394,9 @@ void Assembler::asr_thumb(Register dst, const Operand& src, SBit s, |
void Assembler::and_thumb(Register dst, Register src1, const Operand& src2, |
- SBit s, Condition cond) { |
+ SBitMode smode, Condition cond) { |
ASSERT(cond == al); |
+ SBit s = sbit_from_mode(smode); |
if (!src2.rm_.is_valid()) { |
// Immediate. |
uint32_t i, imm3, imm8; |
@@ -387,12 +408,12 @@ void Assembler::and_thumb(Register dst, Register src1, const Operand& src2, |
return; |
} |
mov_thumb(ip, src2, LeaveCC, al); |
- and_thumb(dst, src1, Operand(ip), s, al); |
+ and_thumb(dst, src1, Operand(ip), smode, al); |
return; |
} else { |
// Register. |
if (dst.code() == src1.code() && are_low_reg(src1, src2.rm_) && |
- s == SetCC && src2.shift_imm_ == 0) { |
+ smode != LeaveCC && src2.shift_imm_ == 0) { |
emit16(thumb16_mode2(AND_REG) | |
thumb16_2lowreg_encoding(dst, src2)); |
return; |
@@ -406,8 +427,9 @@ void Assembler::and_thumb(Register dst, Register src1, const Operand& src2, |
void Assembler::eor_thumb(Register dst, Register src1, const Operand& src2, |
- SBit s, Condition cond) { |
+ SBitMode smode, Condition cond) { |
ASSERT(cond == al); |
+ SBit s = sbit_from_mode(smode); |
if (!src2.rm_.is_valid()) { |
// Immediate. |
uint32_t i, imm3, imm8; |
@@ -416,12 +438,12 @@ void Assembler::eor_thumb(Register dst, Register src1, const Operand& src2, |
return; |
} |
mov_thumb(ip, src2, LeaveCC, al); |
- eor_thumb(dst, src1, Operand(ip), s, al); |
+ eor_thumb(dst, src1, Operand(ip), smode, al); |
return; |
} else { |
// Register. |
if (dst.code() == src1.code() && are_low_reg(src1, src2.rm_) && |
- s == SetCC && src2.shift_imm_ == 0) { |
+ smode != LeaveCC && src2.shift_imm_ == 0) { |
emit16(thumb16_mode2(EOR_REG) | |
thumb16_2lowreg_encoding(dst, src2)); |
return; |
@@ -435,8 +457,9 @@ void Assembler::eor_thumb(Register dst, Register src1, const Operand& src2, |
void Assembler::adc_thumb(Register dst, Register src1, const Operand& src2, |
- SBit s, Condition cond) { |
+ SBitMode smode, Condition cond) { |
ASSERT(cond == al); |
+ SBit s = sbit_from_mode(smode); |
if (!src2.rm_.is_valid()) { |
// Immediate. |
uint32_t i, imm3, imm8; |
@@ -445,12 +468,12 @@ void Assembler::adc_thumb(Register dst, Register src1, const Operand& src2, |
return; |
} |
mov_thumb(ip, src2, LeaveCC, al); |
- adc_thumb(dst, src1, Operand(ip), s, al); |
+ adc_thumb(dst, src1, Operand(ip), smode, al); |
return; |
} else { |
// Register. |
if (dst.code() == src1.code() && are_low_reg(src1, src2.rm_) && |
- s == SetCC && src2.shift_imm_ == 0) { |
+ smode != LeaveCC && src2.shift_imm_ == 0) { |
emit16(thumb16_mode2(ADC_REG) | |
thumb16_2lowreg_encoding(dst, src2)); |
return; |
@@ -464,8 +487,9 @@ void Assembler::adc_thumb(Register dst, Register src1, const Operand& src2, |
void Assembler::sbc_thumb(Register dst, Register src1, const Operand& src2, |
- SBit s, Condition cond) { |
+ SBitMode smode, Condition cond) { |
ASSERT(cond == al); |
+ SBit s = sbit_from_mode(smode); |
if (!src2.rm_.is_valid()) { |
// Immediate. |
uint32_t i, imm3, imm8; |
@@ -474,12 +498,12 @@ void Assembler::sbc_thumb(Register dst, Register src1, const Operand& src2, |
return; |
} |
mov_thumb(ip, src2, LeaveCC, al); |
- sbc_thumb(dst, src1, Operand(ip), s, al); |
+ sbc_thumb(dst, src1, Operand(ip), smode, al); |
return; |
} else { |
// Register. |
if (dst.code() == src1.code() && are_low_reg(src1, src2.rm_) && |
- s == SetCC && src2.shift_imm_ == 0) { |
+ smode != LeaveCC && src2.shift_imm_ == 0) { |
emit16(thumb16_mode2(SBC_REG) | |
thumb16_2lowreg_encoding(dst, src2)); |
return; |
@@ -493,11 +517,14 @@ void Assembler::sbc_thumb(Register dst, Register src1, const Operand& src2, |
void Assembler::rsb_thumb(Register dst, Register src1, const Operand& src2, |
- SBit s, Condition cond) { |
- emit_it(cond); |
+ SBitMode smode, Condition cond) { |
+ bool is_in_it_block = emit_it(cond); |
+ SBit s = sbit_from_mode(smode); |
if (!src2.rm_.is_valid()) { |
// Immediate. |
- if (src2.imm32_ == 0 && are_low_reg(dst, src1)) { |
+ if (it_block_smode_check(is_in_it_block, smode) && |
+ src2.imm32_ == 0 && |
+ are_low_reg(dst, src1)) { |
emit16(thumb16_mode2(RSB_IMM) | |
thumb16_2lowreg_encoding(dst, src1)); |
return; |
@@ -509,7 +536,7 @@ void Assembler::rsb_thumb(Register dst, Register src1, const Operand& src2, |
} |
ASSERT(cond == al); |
mov_thumb(ip, src2, LeaveCC, al); |
- rsb_thumb(dst, src1, Operand(ip), s, al); |
+ rsb_thumb(dst, src1, Operand(ip), smode, al); |
return; |
} |
} else { |
@@ -577,8 +604,9 @@ void Assembler::cmn_thumb(Register src1, const Operand& src2, Condition cond) { |
void Assembler::bic_thumb(Register dst, Register src1, const Operand& src2, |
- SBit s, Condition cond) { |
+ SBitMode smode, Condition cond) { |
ASSERT(cond == al); |
+ SBit s = sbit_from_mode(smode); |
if (!src2.rm_.is_valid()) { |
// Immediate. |
uint32_t i, imm3, imm8; |
@@ -587,12 +615,12 @@ void Assembler::bic_thumb(Register dst, Register src1, const Operand& src2, |
return; |
} |
mov_thumb(ip, src2, LeaveCC, al); |
- bic_thumb(dst, src1, Operand(ip), s, al); |
+ bic_thumb(dst, src1, Operand(ip), smode, al); |
return; |
} else { |
// Register. |
if (dst.code() == src1.code() && are_low_reg(src1, src2.rm_) && |
- s == SetCC && src2.shift_imm_ == 0) { |
+ smode != LeaveCC && src2.shift_imm_ == 0) { |
emit16(thumb16_mode2(BIC_REG) | |
thumb16_2lowreg_encoding(dst, src2)); |
return; |
@@ -606,18 +634,20 @@ void Assembler::bic_thumb(Register dst, Register src1, const Operand& src2, |
void Assembler::mul_thumb(Register dst, Register src1, Register src2, |
- SBit s, Condition cond) { |
+ SBitMode smode, Condition cond) { |
ASSERT(cond == al); |
- if (dst.code() == src2.code() && are_low_reg(src1, src2) && s == SetCC) { |
+ if (dst.code() == src2.code() && are_low_reg(src1, src2) && |
+ smode != LeaveCC) { |
emit16(thumb16_mode2(MUL_REG) | |
thumb16_2lowreg_encoding(dst, src1)); |
return; |
} else if (dst.code() == src1.code() && are_low_reg(src1, src2) && |
- s == SetCC) { |
+ smode != LeaveCC) { |
emit16(thumb16_mode2(MUL_REG) | |
thumb16_2lowreg_encoding(dst, src2)); |
return; |
} else { |
+ SBit s = sbit_from_mode(smode); |
mul_t2(dst, src1, src2, s, cond); |
return; |
} |
@@ -625,9 +655,10 @@ void Assembler::mul_thumb(Register dst, Register src1, Register src2, |
} |
-void Assembler::mvn_thumb(Register dst, const Operand& src, SBit s, |
+void Assembler::mvn_thumb(Register dst, const Operand& src, SBitMode smode, |
Condition cond) { |
ASSERT(cond == al); |
+ SBit s = sbit_from_mode(smode); |
if (!src.rm_.is_valid()) { |
// Immediate. |
uint32_t i, imm3, imm8; |
@@ -636,11 +667,11 @@ void Assembler::mvn_thumb(Register dst, const Operand& src, SBit s, |
return; |
} |
mov_thumb(ip, src, LeaveCC, al); |
- rsb_thumb(dst, ip, Operand(0), s, al); |
+ rsb_thumb(dst, ip, Operand(0), smode, al); |
return; |
} else { |
// Register. |
- if (are_low_reg(dst, src.rm_) && s == SetCC && src.shift_imm_ == 0) { |
+ if (are_low_reg(dst, src.rm_) && smode != LeaveCC && src.shift_imm_ == 0) { |
emit16(thumb16_mode2(MVN_REG) | |
thumb16_2anyreg_encoding(dst, src)); |
return; |
@@ -654,8 +685,9 @@ void Assembler::mvn_thumb(Register dst, const Operand& src, SBit s, |
void Assembler::orr_thumb(Register dst, Register src1, const Operand& src2, |
- SBit s, Condition cond) { |
+ SBitMode smode, Condition cond) { |
ASSERT(cond == al); |
+ SBit s = sbit_from_mode(smode); |
if (!src2.rm_.is_valid()) { |
// Immediate. |
uint32_t i, imm3, imm8; |
@@ -664,19 +696,19 @@ void Assembler::orr_thumb(Register dst, Register src1, const Operand& src2, |
return; |
} |
mov_thumb(ip, src2, LeaveCC, al); |
- orr_thumb(dst, src1, Operand(ip), s, al); |
+ orr_thumb(dst, src1, Operand(ip), smode, al); |
return; |
} else { |
// Register. |
if (dst.code() == src1.code() && are_low_reg(src1, src2.rm_) && |
- s == SetCC && src2.shift_imm_ == 0) { |
+ smode != LeaveCC && src2.shift_imm_ == 0) { |
emit16(thumb16_mode2(ORR_REG) | |
thumb16_2lowreg_encoding(dst, src2)); |
return; |
} else if (src2.rs_.is_valid()) { |
ASSERT(src2.shift_op_ == LSL); |
- lsl_thumb(dst, src2, s, cond); |
- orr_thumb(dst, src1, Operand(dst), s, cond); |
+ lsl_thumb(dst, src2, smode, cond); |
+ orr_thumb(dst, src1, Operand(dst), smode, cond); |
return; |
} else { |
orr_reg_t2(dst, src1, src2, s, cond); |
@@ -1251,8 +1283,8 @@ void Assembler::ldrsh_thumb_register(Register dst, const MemOperand& src) { |
void Assembler::mla_thumb(Register dst, Register src1, Register src2, |
- Register srcA, SBit s, Condition cond) { |
- ASSERT(cond == al && s == LeaveCC); |
+ Register srcA, SBitMode smode, Condition cond) { |
+ ASSERT(cond == al && smode != SetCC); |
emit32(thumb32_mode16(MLA_32) | |
thumb32_4reg(dst, src1, src2, srcA)); |
} |
@@ -1275,32 +1307,32 @@ void Assembler::sdiv_thumb(Register dst, Register src1, Register src2, |
void Assembler::smlal_thumb(Register dstL, Register dstH, Register src1, |
- Register src2, SBit s, Condition cond) { |
- ASSERT(cond == al && s == LeaveCC); |
+ Register src2, SBitMode smode, Condition cond) { |
+ ASSERT(cond == al && smode != SetCC); |
ASSERT(dstL.code() != dstH.code()); |
emit32(thumb32_mode17(SMLAL_32) | thumb32_4reg(dstH, src1, src2, dstL)); |
} |
void Assembler::smull_thumb(Register dstL, Register dstH, Register src1, |
- Register src2, SBit s, Condition cond) { |
- ASSERT(cond == al && s == LeaveCC); |
+ Register src2, SBitMode smode, Condition cond) { |
+ ASSERT(cond == al && smode != SetCC); |
ASSERT(dstL.code() != dstH.code()); |
emit32(thumb32_mode17(SMULL_32) | thumb32_4reg(dstH, src1, src2, dstL)); |
} |
void Assembler::umlal_thumb(Register dstL, Register dstH, Register src1, |
- Register src2, SBit s, Condition cond) { |
- ASSERT(cond == al && s == LeaveCC); |
+ Register src2, SBitMode smode, Condition cond) { |
+ ASSERT(cond == al && smode != SetCC); |
ASSERT(dstL.code() != dstH.code()); |
emit32(thumb32_mode17(UMLAL_32) | thumb32_4reg(dstH, src1, src2, dstL)); |
} |
void Assembler::umull_thumb(Register dstL, Register dstH, Register src1, |
- Register src2, SBit s, Condition cond) { |
- ASSERT(cond == al && s == LeaveCC); |
+ Register src2, SBitMode smode, Condition cond) { |
+ ASSERT(cond == al && smode != SetCC); |
ASSERT(dstL.code() != dstH.code()); |
emit32(thumb32_mode17(UMULL_32) | thumb32_4reg(dstH, src1, src2, dstL)); |
} |