[SubZero] Generate relocations for MIPS

[SubZero] Generate relocations for MIPS

The patch generate Hi, Lo, Jal and data relocations. Instruction encoding of instructions like ldc1, sdc1 etc. has been added.

Following tests from cross-test framework were tested successfully: (non-vector, OBJ mode, Om1, O2)

mem_intrin
TotalTests=114300 Passes=114300 Failures=0

simple_loop
TotalTests=102 Passes=102 Failures=0

test_arith
TotalTests=49489704 Passes=49489704 Failures=0

test_bitmanip
TotalTests=1200 Passes=1200 Failures=0

test_cast
TotalTests=7444 Passes=7444 Failures=0

test_fcmp
TotalTests=123904 Passes=123904 Failures=0

test_global
TotalTests=270 Passes=270 Failures=0

test_icmp
TotalTests=3341520 Passes=3341520 Failures=0

test_strengthreduce
TotalTests=240 Passes=240 Failures=0

Following tests are disabled as they are either all-vectors or contain unimplemented intrinsic lowering:

test_calling_conv
test_select
test_stacksave
test_sync_atomic
test_vector_ops

R=stichnot@chromium.org

Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=130aca718ed16be20e616e591a53de1d69f00d12

[jaydeep.patil, 2016-10-26 13:33:42]

Description was changed from

==========
[SubZero] Generate relocations for MIPS

The patch generate Hi, Lo, Jal and data relocations. Instruction encoding of
instructions like ldc1, sdc1 etc. has been added.
==========

to

==========
[SubZero] Generate relocations for MIPS

The patch generate Hi, Lo, Jal and data relocations. Instruction encoding of
instructions like ldc1, sdc1 etc. has been added.

Following tests from cross-test framework were tested successfully: (non-vector,
OBJ mode, Om1, O2)

mem_intrin
TotalTests=114300 Passes=114300 Failures=0

simple_loop
TotalTests=102 Passes=102 Failures=0

test_arith
TotalTests=49489704 Passes=49489704 Failures=0

test_bitmanip
TotalTests=1200 Passes=1200 Failures=0

test_cast
TotalTests=7444 Passes=7444 Failures=0

test_fcmp
TotalTests=123904 Passes=123904 Failures=0

test_global
TotalTests=270 Passes=270 Failures=0

test_icmp
TotalTests=3341520 Passes=3341520 Failures=0

test_strengthreduce
TotalTests=240 Passes=240 Failures=0

Following tests are disabled as they are either all-vectors or contain
unimplemented intrinsic lowering:

test_calling_conv
test_select
test_stacksave
test_sync_atomic
test_vector_ops
==========

[jaydeep.patil, 2016-10-26 13:33:42]

jaydeep.patil@imgtec.com changed reviewers:
+ eholk@chromium.org, jpp@chromium.org, kschimpf@google.com,
makdstefan@gmail.com, sagar.thakur@imgtec.com, stichnot@chromium.org

[Jim Stichnoth, 2016-10-27 13:58:15]

https://codereview.chromium.org/2446273003/diff/20001/src/IceAssemblerMIPS32.cpp
File src/IceAssemblerMIPS32.cpp (right):

https://codereview.chromium.org/2446273003/diff/20001/src/IceAssemblerMIPS32....
src/IceAssemblerMIPS32.cpp:239: } else {
else if ( ... ) ...

I think that pattern is easier to follow.

Here and several places below.

https://codereview.chromium.org/2446273003/diff/20001/src/IceAssemblerMIPS32....
src/IceAssemblerMIPS32.cpp:586: if (Reloc == RelocOp::RO_Hi) {
Would it be better to use a switch on Reloc here?

https://codereview.chromium.org/2446273003/diff/20001/src/IceInstMIPS32.h
File src/IceInstMIPS32.h (right):

https://codereview.chromium.org/2446273003/diff/20001/src/IceInstMIPS32.h#new...
src/IceInstMIPS32.h:190: Addi,
If we're keeping these lists sorted alphabetically, shouldn't Addi be right
before Addiu?

(This comment also applies to addiu in several other files.)

https://codereview.chromium.org/2446273003/diff/20001/src/IceInstMIPS32.h#new...
src/IceInstMIPS32.h:1307: template <> void InstMIPS32Ldc1::emitIAS(const Cfg
*Func) const;
Move this before Lui to be alphabetized?

[jaydeep.patil, 2016-10-28 02:53:57]

https://codereview.chromium.org/2446273003/diff/20001/src/IceAssemblerMIPS32.cpp
File src/IceAssemblerMIPS32.cpp (right):

https://codereview.chromium.org/2446273003/diff/20001/src/IceAssemblerMIPS32....
src/IceAssemblerMIPS32.cpp:239: } else {
On 2016/10/27 13:58:15, Jim Stichnoth wrote:
> else if ( ... ) ...
> 
> I think that pattern is easier to follow.
> 
> Here and several places below.

Done.

https://codereview.chromium.org/2446273003/diff/20001/src/IceAssemblerMIPS32....
src/IceAssemblerMIPS32.cpp:586: if (Reloc == RelocOp::RO_Hi) {
On 2016/10/27 13:58:15, Jim Stichnoth wrote:
> Would it be better to use a switch on Reloc here?

Done.

https://codereview.chromium.org/2446273003/diff/20001/src/IceInstMIPS32.h
File src/IceInstMIPS32.h (right):

https://codereview.chromium.org/2446273003/diff/20001/src/IceInstMIPS32.h#new...
src/IceInstMIPS32.h:190: Addi,
On 2016/10/27 13:58:15, Jim Stichnoth wrote:
> If we're keeping these lists sorted alphabetically, shouldn't Addi be right
> before Addiu?
> 
> (This comment also applies to addiu in several other files.)

Done.

https://codereview.chromium.org/2446273003/diff/20001/src/IceInstMIPS32.h#new...
src/IceInstMIPS32.h:1307: template <> void InstMIPS32Ldc1::emitIAS(const Cfg
*Func) const;
On 2016/10/27 13:58:15, Jim Stichnoth wrote:
> Move this before Lui to be alphabetized?

Done.

[Jim Stichnoth, 2016-10-28 12:30:45]

lgtm

[Jim Stichnoth, 2016-10-28 12:30:57]

Description was changed from

==========
[SubZero] Generate relocations for MIPS

The patch generate Hi, Lo, Jal and data relocations. Instruction encoding of
instructions like ldc1, sdc1 etc. has been added.

Following tests from cross-test framework were tested successfully: (non-vector,
OBJ mode, Om1, O2)

mem_intrin
TotalTests=114300 Passes=114300 Failures=0

simple_loop
TotalTests=102 Passes=102 Failures=0

test_arith
TotalTests=49489704 Passes=49489704 Failures=0

test_bitmanip
TotalTests=1200 Passes=1200 Failures=0

test_cast
TotalTests=7444 Passes=7444 Failures=0

test_fcmp
TotalTests=123904 Passes=123904 Failures=0

test_global
TotalTests=270 Passes=270 Failures=0

test_icmp
TotalTests=3341520 Passes=3341520 Failures=0

test_strengthreduce
TotalTests=240 Passes=240 Failures=0

Following tests are disabled as they are either all-vectors or contain
unimplemented intrinsic lowering:

test_calling_conv
test_select
test_stacksave
test_sync_atomic
test_vector_ops
==========

to

==========
[SubZero] Generate relocations for MIPS

The patch generate Hi, Lo, Jal and data relocations. Instruction encoding of
instructions like ldc1, sdc1 etc. has been added.

Following tests from cross-test framework were tested successfully: (non-vector,
OBJ mode, Om1, O2)

mem_intrin
TotalTests=114300 Passes=114300 Failures=0

simple_loop
TotalTests=102 Passes=102 Failures=0

test_arith
TotalTests=49489704 Passes=49489704 Failures=0

test_bitmanip
TotalTests=1200 Passes=1200 Failures=0

test_cast
TotalTests=7444 Passes=7444 Failures=0

test_fcmp
TotalTests=123904 Passes=123904 Failures=0

test_global
TotalTests=270 Passes=270 Failures=0

test_icmp
TotalTests=3341520 Passes=3341520 Failures=0

test_strengthreduce
TotalTests=240 Passes=240 Failures=0

Following tests are disabled as they are either all-vectors or contain
unimplemented intrinsic lowering:

test_calling_conv
test_select
test_stacksave
test_sync_atomic
test_vector_ops

R=stichnot@chromium.org

Committed:
https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a...
==========

[Jim Stichnoth, 2016-10-28 12:30:59]

Committed patchset #3 (id:40001) manually as
130aca718ed16be20e616e591a53de1d69f00d12 (presubmit successful).