Subzero, MIPS32: DIVU instruction encoding

src/IceAssemblerMIPS32.cpp

Index: src/IceAssemblerMIPS32.cpp
diff --git a/src/IceAssemblerMIPS32.cpp b/src/IceAssemblerMIPS32.cpp
index a3de7300e4ad6310a8a61d3cefb8490bd4226d5d..5d56cffd2289ad43c629c59754d4cc1b66e6e359 100644
--- a/src/IceAssemblerMIPS32.cpp
+++ b/src/IceAssemblerMIPS32.cpp
@@ -537,6 +537,11 @@ void AssemblerMIPS32::div_s(const Operand *OpFd, const Operand *OpFs,
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "div.s");
 }
 
+void AssemblerMIPS32::divu(const Operand *OpRs, const Operand *OpRt) {
+  static constexpr IValueT Opcode = 0x0000001B;
+  emitRsRt(Opcode, OpRs, OpRt, "divu");
+}
+
 void AssemblerMIPS32::lui(const Operand *OpRt, const uint16_t Imm) {
   IValueT Opcode = 0x3C000000;
   const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui");