Subzero, MIPS32: DIVU instruction encoding

src/IceAssemblerMIPS32.cpp

 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 519 matching lines @@
   static constexpr IValueT Opcode = 0x44000003;
   emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "div.d");
 }
 
 void AssemblerMIPS32::div_s(const Operand *OpFd, const Operand *OpFs,
                             const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000003;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "div.s");
 }
 
+void AssemblerMIPS32::divu(const Operand *OpRs, const Operand *OpRt) {
+  static constexpr IValueT Opcode = 0x0000001B;
+  emitRsRt(Opcode, OpRs, OpRt, "divu");
+}
+
 void AssemblerMIPS32::lui(const Operand *OpRt, const uint16_t Imm) {
   IValueT Opcode = 0x3C000000;
   const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui");
   Opcode |= Rt << 16;
   Opcode |= Imm;
   emitInst(Opcode);
 }
 
 void AssemblerMIPS32::lw(const Operand *OpRt, const Operand *OpBase,
                          const uint32_t Offset) {
@@ skipping 453 matching lines @@
     emitBr(Cond, OpRs, OpRtNone, Dest);
     return;
   }
   const IOffsetT Position = Buffer.size();
   emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition());
   TargetLabel->linkTo(*this, Position);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice