S390: Decouple Add/Sub/Neg to 32/64 Bit Op

src/s390/disasm-s390.cc

Index: src/s390/disasm-s390.cc
diff --git a/src/s390/disasm-s390.cc b/src/s390/disasm-s390.cc
index c8d52f1b230442040f65b30b106093ab9c717bf3..86810927a3a0284cc643f97235cda1e5041836ee 100644
--- a/src/s390/disasm-s390.cc
+++ b/src/s390/disasm-s390.cc
@@ -820,6 +820,12 @@ bool Decoder::DecodeFourByte(Instruction* instr) {
     case LLGHR:
       Format(instr, "llghr\t'r5,'r6");
       break;
+    case LOCR:
+      Format(instr, "locr\t'm1,'r5,'r6");
+      break;
+    case LOCGR:
+      Format(instr, "locgr\t'm1,'r5,'r6");
+      break;
     case LNGR:
       Format(instr, "lngr\t'r5,'r6");
       break;
@@ -1130,6 +1136,12 @@ bool Decoder::DecodeSixByte(Instruction* instr) {
     case RISBGN:
       Format(instr, "risbgn\t'r1,'r2,'i9,'ia,'ib");
       break;
+    case LOCG:
+      Format(instr, "locg\t'm2,'r1,'d2('r3)");
+      break;
+    case LOC:
+      Format(instr, "loc\t'm2,'r1,'d2('r3)");
+      break;
     case LMY:
       Format(instr, "lmy\t'r1,'r2,'d2('r3)");
       break;