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Issue 2220313002: S390: Decouple Add/Sub/Neg to 32/64 Bit Op (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix Neg32 to use lcr Created 4 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // A Disassembler object is used to disassemble a block of code instruction by 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be 6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses. 7 // overriden to modify register names or to do symbol lookup on addresses.
8 // 8 //
9 // The example below will disassemble a block of code and print it to stdout. 9 // The example below will disassemble a block of code and print it to stdout.
10 // 10 //
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813 break; 813 break;
814 case LHR: 814 case LHR:
815 Format(instr, "lhr\t'r5,'r6"); 815 Format(instr, "lhr\t'r5,'r6");
816 break; 816 break;
817 case LLHR: 817 case LLHR:
818 Format(instr, "llhr\t'r5,'r6"); 818 Format(instr, "llhr\t'r5,'r6");
819 break; 819 break;
820 case LLGHR: 820 case LLGHR:
821 Format(instr, "llghr\t'r5,'r6"); 821 Format(instr, "llghr\t'r5,'r6");
822 break; 822 break;
823 case LOCR:
824 Format(instr, "locr\t'm1,'r5,'r6");
825 break;
826 case LOCGR:
827 Format(instr, "locgr\t'm1,'r5,'r6");
828 break;
823 case LNGR: 829 case LNGR:
824 Format(instr, "lngr\t'r5,'r6"); 830 Format(instr, "lngr\t'r5,'r6");
825 break; 831 break;
826 case A: 832 case A:
827 Format(instr, "a\t'r1,'d1('r2d,'r3)"); 833 Format(instr, "a\t'r1,'d1('r2d,'r3)");
828 break; 834 break;
829 case S: 835 case S:
830 Format(instr, "s\t'r1,'d1('r2d,'r3)"); 836 Format(instr, "s\t'r1,'d1('r2d,'r3)");
831 break; 837 break;
832 case M: 838 case M:
(...skipping 290 matching lines...) Expand 10 before | Expand all | Expand 10 after
1123 break; 1129 break;
1124 case SRAG: 1130 case SRAG:
1125 Format(instr, "srag\t'r1,'r2,'d2('r3)"); 1131 Format(instr, "srag\t'r1,'r2,'d2('r3)");
1126 break; 1132 break;
1127 case RISBG: 1133 case RISBG:
1128 Format(instr, "risbg\t'r1,'r2,'i9,'ia,'ib"); 1134 Format(instr, "risbg\t'r1,'r2,'i9,'ia,'ib");
1129 break; 1135 break;
1130 case RISBGN: 1136 case RISBGN:
1131 Format(instr, "risbgn\t'r1,'r2,'i9,'ia,'ib"); 1137 Format(instr, "risbgn\t'r1,'r2,'i9,'ia,'ib");
1132 break; 1138 break;
1139 case LOCG:
1140 Format(instr, "locg\t'm2,'r1,'d2('r3)");
1141 break;
1142 case LOC:
1143 Format(instr, "loc\t'm2,'r1,'d2('r3)");
1144 break;
1133 case LMY: 1145 case LMY:
1134 Format(instr, "lmy\t'r1,'r2,'d2('r3)"); 1146 Format(instr, "lmy\t'r1,'r2,'d2('r3)");
1135 break; 1147 break;
1136 case LMG: 1148 case LMG:
1137 Format(instr, "lmg\t'r1,'r2,'d2('r3)"); 1149 Format(instr, "lmg\t'r1,'r2,'d2('r3)");
1138 break; 1150 break;
1139 case STMY: 1151 case STMY:
1140 Format(instr, "stmy\t'r1,'r2,'d2('r3)"); 1152 Format(instr, "stmy\t'r1,'r2,'d2('r3)");
1141 break; 1153 break;
1142 case STMG: 1154 case STMG:
(...skipping 304 matching lines...) Expand 10 before | Expand all | Expand 10 after
1447 byte* prev_pc = pc; 1459 byte* prev_pc = pc;
1448 pc += d.InstructionDecode(buffer, pc); 1460 pc += d.InstructionDecode(buffer, pc);
1449 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc), 1461 v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc),
1450 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1462 *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1451 } 1463 }
1452 } 1464 }
1453 1465
1454 } // namespace disasm 1466 } // namespace disasm
1455 1467
1456 #endif // V8_TARGET_ARCH_S390 1468 #endif // V8_TARGET_ARCH_S390
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