S390: Decouple Add/Sub/Neg to 32/64 Bit Op

src/s390/assembler-s390.cc

Index: src/s390/assembler-s390.cc
diff --git a/src/s390/assembler-s390.cc b/src/s390/assembler-s390.cc
index 673ef61b0de94dffb6579dc9c30c6ae8855581ed..6dbb1ed77dfa01df5f4bb09f9b2d5ab9deaeabf6 100644
--- a/src/s390/assembler-s390.cc
+++ b/src/s390/assembler-s390.cc
@@ -971,6 +971,20 @@ void Assembler::rxy_form(Opcode op, Register r1, Register x2, Register b2,
   emit6bytes(code);
 }
 
+void Assembler::rxy_form(Opcode op, Register r1, Condition m3, Register b2,
+                         Disp d2) {
+  DCHECK(is_int20(d2));
+  DCHECK(is_uint16(op));
+  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
+                  (static_cast<uint64_t>(r1.code())) * B36 |
+                  (static_cast<uint64_t>(m3 & 0xF)) * B32 |
+                  (static_cast<uint64_t>(b2.code())) * B28 |
+                  (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
+                  (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 |
+                  (static_cast<uint64_t>(op & 0x00FF));
+  emit6bytes(code);
+}
+
 void Assembler::rxy_form(Opcode op, DoubleRegister r1, Register x2, Register b2,
                          Disp d2) {
   DCHECK(is_int20(d2));
@@ -1418,7 +1432,6 @@ RIL1_FORM_EMIT(llihf, LLIHF)
 RIL1_FORM_EMIT(llilf, LLILF)
 RRE_FORM_EMIT(lngr, LNGR)
 RR_FORM_EMIT(lnr, LNR)
-RSY1_FORM_EMIT(loc, LOC)
 RRE_FORM_EMIT(lrvr, LRVR)
 RRE_FORM_EMIT(lrvgr, LRVGR)
 RXY_FORM_EMIT(lrv, LRV)
@@ -1604,6 +1617,26 @@ void Assembler::llhr(Register r1, Register r2) { rre_form(LLHR, r1, r2); }
 // Load Logical halfword Register-Register (64)
 void Assembler::llghr(Register r1, Register r2) { rre_form(LLGHR, r1, r2); }
 
+// Load On Condition R-R (32)
+void Assembler::locr(Condition m3, Register r1, Register r2) {
+  rrf2_form(LOCR << 16 | m3 * B12 | r1.code() * B4 | r2.code());
+}
+
+// Load On Condition R-R (64)
+void Assembler::locgr(Condition m3, Register r1, Register r2) {
+  rrf2_form(LOCGR << 16 | m3 * B12 | r1.code() * B4 | r2.code());
+}
+
+// Load On Condition R-M (32)
+void Assembler::loc(Condition m3, Register r1, const MemOperand& src) {
+  rxy_form(LOC, r1, m3, src.rb(), src.offset());
+}
+
+// Load On Condition R-M (64)
+void Assembler::locg(Condition m3, Register r1, const MemOperand& src) {
+  rxy_form(LOCG, r1, m3, src.rb(), src.offset());
+}
+
 // -------------------
 // Branch Instructions
 // -------------------