S390: Decouple Add/Sub/Neg to 32/64 Bit Op

src/s390/assembler-s390.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 953 matching lines @@
   uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                   (static_cast<uint64_t>(r1.code())) * B36 |
                   (static_cast<uint64_t>(x2.code())) * B32 |
                   (static_cast<uint64_t>(b2.code())) * B28 |
                   (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
                   (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 |
                   (static_cast<uint64_t>(op & 0x00FF));
   emit6bytes(code);
 }
 
+void Assembler::rxy_form(Opcode op, Register r1, Condition m3, Register b2,
+                         Disp d2) {
+  DCHECK(is_int20(d2));
+  DCHECK(is_uint16(op));
+  uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
+                  (static_cast<uint64_t>(r1.code())) * B36 |
+                  (static_cast<uint64_t>(m3 & 0xF)) * B32 |
+                  (static_cast<uint64_t>(b2.code())) * B28 |
+                  (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
+                  (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 |
+                  (static_cast<uint64_t>(op & 0x00FF));
+  emit6bytes(code);
+}
+
 void Assembler::rxy_form(Opcode op, DoubleRegister r1, Register x2, Register b2,
                          Disp d2) {
   DCHECK(is_int20(d2));
   DCHECK(is_uint16(op));
   uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                   (static_cast<uint64_t>(r1.code())) * B36 |
                   (static_cast<uint64_t>(x2.code())) * B32 |
                   (static_cast<uint64_t>(b2.code())) * B28 |
                   (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
                   (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 |
@@ skipping 427 matching lines @@
 RX_FORM_EMIT(ex, EX)
 RRE_FORM_EMIT(flogr, FLOGR)
 RRE_FORM_EMIT(lcgr, LCGR)
 RR_FORM_EMIT(lcr, LCR)
 RX_FORM_EMIT(le_z, LE)
 RXY_FORM_EMIT(ley, LEY)
 RIL1_FORM_EMIT(llihf, LLIHF)
 RIL1_FORM_EMIT(llilf, LLILF)
 RRE_FORM_EMIT(lngr, LNGR)
 RR_FORM_EMIT(lnr, LNR)
-RSY1_FORM_EMIT(loc, LOC)
 RRE_FORM_EMIT(lrvr, LRVR)
 RRE_FORM_EMIT(lrvgr, LRVGR)
 RXY_FORM_EMIT(lrv, LRV)
 RXY_FORM_EMIT(lrvg, LRVG)
 RXY_FORM_EMIT(lrvh, LRVH)
 SS1_FORM_EMIT(mvn, MVN)
 SS1_FORM_EMIT(nc, NC)
 SI_FORM_EMIT(ni, NI)
 RIL1_FORM_EMIT(nihf, NIHF)
 RIL1_FORM_EMIT(nilf, NILF)
@@ skipping 165 matching lines @@
 void Assembler::llgh(Register r1, const MemOperand& opnd) {
   rxy_form(LLGH, r1, opnd.rx(), opnd.rb(), opnd.offset());
 }
 
 // Load Logical halfword Register-Register (32)
 void Assembler::llhr(Register r1, Register r2) { rre_form(LLHR, r1, r2); }
 
 // Load Logical halfword Register-Register (64)
 void Assembler::llghr(Register r1, Register r2) { rre_form(LLGHR, r1, r2); }
 
+// Load On Condition R-R (32)
+void Assembler::locr(Condition m3, Register r1, Register r2) {
+  rrf2_form(LOCR << 16 | m3 * B12 | r1.code() * B4 | r2.code());
+}
+
+// Load On Condition R-R (64)
+void Assembler::locgr(Condition m3, Register r1, Register r2) {
+  rrf2_form(LOCGR << 16 | m3 * B12 | r1.code() * B4 | r2.code());
+}
+
+// Load On Condition R-M (32)
+void Assembler::loc(Condition m3, Register r1, const MemOperand& src) {
+  rxy_form(LOC, r1, m3, src.rb(), src.offset());
+}
+
+// Load On Condition R-M (64)
+void Assembler::locg(Condition m3, Register r1, const MemOperand& src) {
+  rxy_form(LOCG, r1, m3, src.rb(), src.offset());
+}
+
 // -------------------
 // Branch Instructions
 // -------------------
 // Branch and Save
 void Assembler::basr(Register r1, Register r2) { rr_form(BASR, r1, r2); }
 
 // Indirect Conditional Branch via register
 void Assembler::bcr(Condition m, Register target) { rr_form(BCR, m, target); }
 
 // Branch on Count (32)
@@ skipping 1462 matching lines @@
                             SKIP_ICACHE_FLUSH);
     }
 
     reloc_info_writer.Write(&rinfo);
   }
 }
 
 }  // namespace internal
 }  // namespace v8
 #endif  // V8_TARGET_ARCH_S390