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Unified Diff: src/IceInstARM32.def

Issue 1881623002: Subzero. ARM32. Vector shifts. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Pre-review pass. Created 4 years, 8 months ago
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« src/IceInstARM32.cpp ('K') | « src/IceInstARM32.cpp ('k') | src/IceTargetLoweringARM32.h » ('j') | tests_lit/assembler/arm32/asr.ll » ('J')
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Index: src/IceInstARM32.def
diff --git a/src/IceInstARM32.def b/src/IceInstARM32.def
index 003449903f73f566d0b9099d874f5d579b3c71b0..c1074abc659dd176fe8aa6c2d1c992c8ec548ff7 100644
--- a/src/IceInstARM32.def
+++ b/src/IceInstARM32.def
@@ -70,24 +70,24 @@
// the # of offset bits allowed as part of an addressing mode (for sign or zero
// extending load/stores).
#define ICETYPEARM32_TABLE \
- /* tag, element type, int_width, vec_width, addr bits sext, zext, \
- reg-reg addr allowed, shift allowed, */ \
- X(IceType_void, IceType_void, "" , "" , 0 , 0 , 0, 0) \
- X(IceType_i1, IceType_void, "b", "" , 8 , 12, 1, 1) \
- X(IceType_i8, IceType_void, "b", "" , 8 , 12, 1, 1) \
- X(IceType_i16, IceType_void, "h", "" , 8 , 8 , 1, 0) \
- X(IceType_i32, IceType_void, "" , "" , 12, 12, 1, 1) \
- X(IceType_i64, IceType_void, "d", "" , 12, 12, 1, 1) \
- X(IceType_f32, IceType_void, "" , ".f32", 8, 8 , 0, 0) \
- X(IceType_f64, IceType_void, "" , ".f64", 8, 8 , 0, 0) \
- X(IceType_v4i1, IceType_i32 , "" , ".i32", 0 , 0 , 1, 0) \
- X(IceType_v8i1, IceType_i16 , "" , ".i16", 0 , 0 , 1, 0) \
- X(IceType_v16i1, IceType_i8 , "" , ".i8" , 0 , 0 , 1, 0) \
- X(IceType_v16i8, IceType_i8 , "" , ".i8" , 0 , 0 , 1, 0) \
- X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0 , 1, 0) \
- X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0 , 1, 0) \
- X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0 , 1, 0)
-//#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr, shaddr)
+ /* tag, element type, int_width, fp_width, uvec_width, svec_width, \
+ addr bits sext, zext, reg-reg addr allowed, shift allowed, */ \
+ X(IceType_void, IceType_void, "" , "" , "" , "" , 0 , 0 , 0, 0) \
+ X(IceType_i1, IceType_void, "b", "" , "" , "" , 8 , 12, 1, 1) \
+ X(IceType_i8, IceType_void, "b", "" , "" , "" , 8 , 12, 1, 1) \
+ X(IceType_i16, IceType_void, "h", "" , "" , "" , 8 , 8 , 1, 0) \
+ X(IceType_i32, IceType_void, "" , "" , "" , "" , 12, 12, 1, 1) \
+ X(IceType_i64, IceType_void, "d", "" , "" , "" , 12, 12, 1, 1) \
+ X(IceType_f32, IceType_void, "" , ".f32", "" , "" , 8, 8 , 0, 0) \
+ X(IceType_f64, IceType_void, "" , ".f64", "" , "" , 8, 8 , 0, 0) \
+ X(IceType_v4i1, IceType_i32 , "" , ".i32", ".u32", ".s32", 0 , 0 , 1, 0) \
+ X(IceType_v8i1, IceType_i16 , "" , ".i16", ".u16", ".s16", 0 , 0 , 1, 0) \
+ X(IceType_v16i1, IceType_i8 , "" , ".i8" , ".u8" , ".s8" , 0 , 0 , 1, 0) \
+ X(IceType_v16i8, IceType_i8 , "" , ".i8" , ".u8" , ".s8" , 0 , 0 , 1, 0) \
+ X(IceType_v8i16, IceType_i16 , "" , ".i16", ".u16", ".s16", 0 , 0 , 1, 0) \
+ X(IceType_v4i32, IceType_i32 , "" , ".i32", ".u32", ".s32", 0 , 0 , 1, 0) \
+ X(IceType_v4f32, IceType_f32 , "" , ".f32", ".f32", ".f32", 0 , 0 , 1, 0)
+//#define X(tag, elementty, int_width, fp_width, sbits, ubits, rraddr, shaddr)
Jim Stichnoth 2016/04/13 15:53:24 Update comment to include new macro args.
John 2016/04/15 13:20:56 Done.
// Shifter types for Data-processing operands as defined in section A5.1.2.
#define ICEINSTARM32SHIFT_TABLE \
« src/IceInstARM32.cpp ('K') | « src/IceInstARM32.cpp ('k') | src/IceTargetLoweringARM32.h » ('j') | tests_lit/assembler/arm32/asr.ll » ('J')

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