Subzero. ARM32. Vector shifts.

tests_lit/assembler/arm32/asr.ll

Index: tests_lit/assembler/arm32/asr.ll
diff --git a/tests_lit/assembler/arm32/asr.ll b/tests_lit/assembler/arm32/asr.ll
index 4e9e29ffc464766511650dcf6a5ff7e245de5645..465da01ca54f01acdbc29858c654280af7f0aec8 100644
--- a/tests_lit/assembler/arm32/asr.ll
+++ b/tests_lit/assembler/arm32/asr.ll
@@ -71,14 +71,18 @@ entry:
 
   %v = ashr <4 x i32> %a, %b
 
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; DIS:  28: e1a00150
-; DIS:  38: e1a00150
-; DIS:  48: e1a00150
-; DIS:  58: e1a00150
+; ASM:          vneg.s32  q1, q1
+; ASM-NEXT:     vshl.s32 q0, q0, q1
+; DIS:      20:          f3b923c2

[Karl, 2016/04/13 16:17:36]

No need to check the bytes generated for IASM. the 4th RUN command will check
this using DIS.

Simply check that it wasn't a text fix up. That is:

; IASM-NOT: vneg.s32  q1, q1
; IASM-NOT: vshl.s32 q0, q0, a1

[John, 2016/04/15 13:20:57]

Done.

+; DIS:      24:          f2220440
+; IASM:         .byte 0xc2
+; IASM-NEXT:    .byte 0x23
+; IASM-NEXT:    .byte 0xb9
+; IASM-NEXT:    .byte 0xf3
+; IASM-NEXT:    .byte 0x40
+; IASM-NEXT:    .byte 0x4
+; IASM-NEXT:    .byte 0x22
+; IASM-NEXT:    .byte 0xf2
 
   ret <4 x i32> %v
 }
@@ -90,14 +94,18 @@ entry:
 
   %v = ashr <8 x i16> %a, %b
 
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
+; ASM:          vneg.s16  q1, q1
+; ASM-NEXT:     vshl.s16 q0, q0, q1
+; DIS:      30:          f3b523c2
+; DIS:      34:          f2120440
+; IASM:         .byte 0xc2

[Karl, 2016/04/13 16:17:36]

Same here.

[John, 2016/04/15 13:20:56]

Done.

+; IASM-NEXT:    .byte 0x23
+; IASM-NEXT:    .byte 0xb5
+; IASM-NEXT:    .byte 0xf3
+; IASM-NEXT:    .byte 0x40
+; IASM-NEXT:    .byte 0x4
+; IASM-NEXT:    .byte 0x12
+; IASM-NEXT:    .byte 0xf2
 
   ret <8 x i16> %v
 }
@@ -109,22 +117,18 @@ entry:
 
   %v = ashr <16 x i8> %a, %b
 
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
-; ASM:     asr     r0, r0, r1
+; ASM:          vneg.s8  q1, q1
+; ASM-NEXT:     vshl.s8 q0, q0, q1
+; DIS:      40:         f3b123c2
+; DIS:      44:         f2020440
+; IASM:         .byte 0xc2

[Karl, 2016/04/13 16:17:36]

Same here.

[John, 2016/04/15 13:20:57]

Done.

+; IASM-NEXT:    .byte 0x23
+; IASM-NEXT:    .byte 0xb1
+; IASM-NEXT:    .byte 0xf3
+; IASM-NEXT:    .byte 0x40
+; IASM-NEXT:    .byte 0x4
+; IASM-NEXT:    .byte 0x2
+; IASM-NEXT:    .byte 0xf2
 
   ret <16 x i8> %v
 }