Chromium Code Reviews Chromium Code Reviews
Issue 1881623002:
Subzero. ARM32. Vector shifts. (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master| OLD | NEW |
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| 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// | 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // This file defines properties of ARM32 instructions in the form of x-macros. | 10 // This file defines properties of ARM32 instructions in the form of x-macros. |
| (...skipping 52 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 63 X(Reg_DREG_First, = Reg_d0) \ | 63 X(Reg_DREG_First, = Reg_d0) \ |
| 64 X(Reg_DREG_Last, = Reg_d31) \ | 64 X(Reg_DREG_Last, = Reg_d31) \ |
| 65 X(Reg_QREG_First, = Reg_q0) \ | 65 X(Reg_QREG_First, = Reg_q0) \ |
| 66 X(Reg_QREG_Last, = Reg_q15) | 66 X(Reg_QREG_Last, = Reg_q15) |
| 67 // define X(val, init) | 67 // define X(val, init) |
| 68 | 68 |
| 69 // Load/Store instruction width suffixes and FP/Vector element size suffixes | 69 // Load/Store instruction width suffixes and FP/Vector element size suffixes |
| 70 // the # of offset bits allowed as part of an addressing mode (for sign or zero | 70 // the # of offset bits allowed as part of an addressing mode (for sign or zero |
| 71 // extending load/stores). | 71 // extending load/stores). |
| 72 #define ICETYPEARM32_TABLE \ | 72 #define ICETYPEARM32_TABLE \ |
| 73 /* tag, element type, int_width, vec_width, addr bits sext, zext, \ | 73 /* tag, element type, int_width, fp_width, uvec_width, svec_width, \ |
| 74 reg-reg addr allowed, shift allowed, */ \ | 74 addr bits sext, zext, reg-reg addr allowed, shift allowed, */ \ |
| 75 X(IceType_void, IceType_void, "" , "" , 0 , 0 , 0, 0) \ | 75 X(IceType_void, IceType_void, "" , "" , "" , "" , 0 , 0 , 0, 0) \ |
| 76 X(IceType_i1, IceType_void, "b", "" , 8 , 12, 1, 1) \ | 76 X(IceType_i1, IceType_void, "b", "" , "" , "" , 8 , 12, 1, 1) \ |
| 77 X(IceType_i8, IceType_void, "b", "" , 8 , 12, 1, 1) \ | 77 X(IceType_i8, IceType_void, "b", "" , "" , "" , 8 , 12, 1, 1) \ |
| 78 X(IceType_i16, IceType_void, "h", "" , 8 , 8 , 1, 0) \ | 78 X(IceType_i16, IceType_void, "h", "" , "" , "" , 8 , 8 , 1, 0) \ |
| 79 X(IceType_i32, IceType_void, "" , "" , 12, 12, 1, 1) \ | 79 X(IceType_i32, IceType_void, "" , "" , "" , "" , 12, 12, 1, 1) \ |
| 80 X(IceType_i64, IceType_void, "d", "" , 12, 12, 1, 1) \ | 80 X(IceType_i64, IceType_void, "d", "" , "" , "" , 12, 12, 1, 1) \ |
| 81 X(IceType_f32, IceType_void, "" , ".f32", 8, 8 , 0, 0) \ | 81 X(IceType_f32, IceType_void, "" , ".f32", "" , "" , 8, 8 , 0, 0) \ |
| 82 X(IceType_f64, IceType_void, "" , ".f64", 8, 8 , 0, 0) \ | 82 X(IceType_f64, IceType_void, "" , ".f64", "" , "" , 8, 8 , 0, 0) \ |
| 83 X(IceType_v4i1, IceType_i32 , "" , ".i32", 0 , 0 , 1, 0) \ | 83 X(IceType_v4i1, IceType_i32 , "" , ".i32", ".u32", ".s32", 0 , 0 , 1, 0) \ |
| 84 X(IceType_v8i1, IceType_i16 , "" , ".i16", 0 , 0 , 1, 0) \ | 84 X(IceType_v8i1, IceType_i16 , "" , ".i16", ".u16", ".s16", 0 , 0 , 1, 0) \ |
| 85 X(IceType_v16i1, IceType_i8 , "" , ".i8" , 0 , 0 , 1, 0) \ | 85 X(IceType_v16i1, IceType_i8 , "" , ".i8" , ".u8" , ".s8" , 0 , 0 , 1, 0) \ |
| 86 X(IceType_v16i8, IceType_i8 , "" , ".i8" , 0 , 0 , 1, 0) \ | 86 X(IceType_v16i8, IceType_i8 , "" , ".i8" , ".u8" , ".s8" , 0 , 0 , 1, 0) \ |
| 87 X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0 , 1, 0) \ | 87 X(IceType_v8i16, IceType_i16 , "" , ".i16", ".u16", ".s16", 0 , 0 , 1, 0) \ |
| 88 X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0 , 1, 0) \ | 88 X(IceType_v4i32, IceType_i32 , "" , ".i32", ".u32", ".s32", 0 , 0 , 1, 0) \ |
| 89 X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0 , 1, 0) | 89 X(IceType_v4f32, IceType_f32 , "" , ".f32", ".f32", ".f32", 0 , 0 , 1, 0) |
| 90 //#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr, shaddr) | 90 //#define X(tag, elementty, int_width, fp_width, sbits, ubits, rraddr, shaddr) |
|
Jim Stichnoth
2016/04/13 15:53:24
Update comment to include new macro args.
John
2016/04/15 13:20:56
Done.
| |
| 91 | 91 |
| 92 // Shifter types for Data-processing operands as defined in section A5.1.2. | 92 // Shifter types for Data-processing operands as defined in section A5.1.2. |
| 93 #define ICEINSTARM32SHIFT_TABLE \ | 93 #define ICEINSTARM32SHIFT_TABLE \ |
| 94 /* enum value, emit */ \ | 94 /* enum value, emit */ \ |
| 95 X(LSL, "lsl") \ | 95 X(LSL, "lsl") \ |
| 96 X(LSR, "lsr") \ | 96 X(LSR, "lsr") \ |
| 97 X(ASR, "asr") \ | 97 X(ASR, "asr") \ |
| 98 X(ROR, "ror") \ | 98 X(ROR, "ror") \ |
| 99 X(RRX, "rrx") | 99 X(RRX, "rrx") |
| 100 //#define X(tag, emit) | 100 //#define X(tag, emit) |
| (...skipping 15 matching lines...) Expand all Loading... | |
| 116 X(LS, 9, HI, "ls") /* unsigned lower or same */ \ | 116 X(LS, 9, HI, "ls") /* unsigned lower or same */ \ |
| 117 X(GE, 10, LT, "ge") /* signed greater than or equal */ \ | 117 X(GE, 10, LT, "ge") /* signed greater than or equal */ \ |
| 118 X(LT, 11, GE, "lt") /* signed less than */ \ | 118 X(LT, 11, GE, "lt") /* signed less than */ \ |
| 119 X(GT, 12, LE, "gt") /* signed greater than */ \ | 119 X(GT, 12, LE, "gt") /* signed greater than */ \ |
| 120 X(LE, 13, GT, "le") /* signed less than or equal */ \ | 120 X(LE, 13, GT, "le") /* signed less than or equal */ \ |
| 121 X(AL, 14, kNone, "") /* always (unconditional) */ \ | 121 X(AL, 14, kNone, "") /* always (unconditional) */ \ |
| 122 X(kNone, 15, kNone, "??") /* special condition / none */ | 122 X(kNone, 15, kNone, "??") /* special condition / none */ |
| 123 //#define X(tag, encode, opp, emit) | 123 //#define X(tag, encode, opp, emit) |
| 124 | 124 |
| 125 #endif // SUBZERO_SRC_ICEINSTARM32_DEF | 125 #endif // SUBZERO_SRC_ICEINSTARM32_DEF |
| OLD | NEW |
