Chromium Code Reviews
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Chromium Code Reviews
Issue
1845043004:
[x64] Optimize loading SMIs. (Closed)
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Created:
4 years, 8 months ago by epertoso Modified:
4 years, 8 months ago Reviewers:
Benedikt Meurer CC:
v8-reviews_googlegroups.com Base URL:
https://chromium.googlesource.com/v8/v8.git@master Target Ref:
refs/pending/heads/master Project:
v8 Visibility:
Public. |
Description[x64] Optimize loading SMIs.
Especially when loading and untagging SMIs within code stubs, instances of the following pattern appear in the generated code:
movq %rax,[%rbx+%rcx*4+0xf]
sarq %rax, 32
This CL changes that code to:
movsxlq %rax, [%ebx+%ecx*4+0x13]
BUG=
Committed: https://crrev.com/9ca9195dd4ae363113692347c337f088c998bcd5
Cr-Commit-Position: refs/heads/master@{#35194}
Patch Set 1 #Patch Set 2 : Update. #
Total comments: 2
Patch Set 3 : Update. #
Total comments: 1
Patch Set 4 : Update #Messages
Total messages: 16 (8 generated)
Description was changed from ========== [turbofan] Optize loading SMIs on x64. Especially when loading and untagging SMIs in code stubs, instances of the following pattern appear in the generated code: movq %rax,[%rbx+%rcx*4+0xf] sarq %rax, 32 This CL changes that code to: movsxlq %rax, [%ebx+%ecx*4+0x13] BUG= ========== to ========== [turbofan] Optize loading SMIs on x64. Especially when loading and untagging SMIs within code stubs, instances of the following pattern appear in the generated code: movq %rax,[%rbx+%rcx*4+0xf] sarq %rax, 32 This CL changes that code to: movsxlq %rax, [%ebx+%ecx*4+0x13] BUG= ==========
epertoso@chromium.org changed reviewers: + titzer@chromium.org
epertoso@chromium.org changed reviewers: + bmeurer@chromium.org - titzer@chromium.org
Description was changed from ========== [turbofan] Optize loading SMIs on x64. Especially when loading and untagging SMIs within code stubs, instances of the following pattern appear in the generated code: movq %rax,[%rbx+%rcx*4+0xf] sarq %rax, 32 This CL changes that code to: movsxlq %rax, [%ebx+%ecx*4+0x13] BUG= ========== to ========== [x64] Optize loading SMIs. Especially when loading and untagging SMIs within code stubs, instances of the following pattern appear in the generated code: movq %rax,[%rbx+%rcx*4+0xf] sarq %rax, 32 This CL changes that code to: movsxlq %rax, [%ebx+%ecx*4+0x13] BUG= ==========
Description was changed from ========== [x64] Optize loading SMIs. Especially when loading and untagging SMIs within code stubs, instances of the following pattern appear in the generated code: movq %rax,[%rbx+%rcx*4+0xf] sarq %rax, 32 This CL changes that code to: movsxlq %rax, [%ebx+%ecx*4+0x13] BUG= ========== to ========== [x64] Optimize loading SMIs. Especially when loading and untagging SMIs within code stubs, instances of the following pattern appear in the generated code: movq %rax,[%rbx+%rcx*4+0xf] sarq %rax, 32 This CL changes that code to: movsxlq %rax, [%ebx+%ecx*4+0x13] BUG= ==========
https://codereview.chromium.org/1845043004/diff/20001/src/compiler/x64/instru... File src/compiler/x64/instruction-selector-x64.cc (right): https://codereview.chromium.org/1845043004/diff/20001/src/compiler/x64/instru... src/compiler/x64/instruction-selector-x64.cc:72: DCHECK(mode == kMode_MR || (kMode_MR1 <= mode && mode <= kMode_MR8) || As discussed offline, please do a switch here. And please inline into the callsite.
https://codereview.chromium.org/1845043004/diff/20001/src/compiler/x64/instru... File src/compiler/x64/instruction-selector-x64.cc (right): https://codereview.chromium.org/1845043004/diff/20001/src/compiler/x64/instru... src/compiler/x64/instruction-selector-x64.cc:72: DCHECK(mode == kMode_MR || (kMode_MR1 <= mode && mode <= kMode_MR8) || On 2016/04/01 at 08:33:00, Benedikt Meurer wrote: > As discussed offline, please do a switch here. And please inline into the callsite. Done.
LGTM once comment addressed. https://codereview.chromium.org/1845043004/diff/40001/src/compiler/x64/instru... File src/compiler/x64/instruction-selector-x64.cc (right): https://codereview.chromium.org/1845043004/diff/40001/src/compiler/x64/instru... src/compiler/x64/instruction-selector-x64.cc:665: default: No default please, and use UNREACHABLE for cases that don't make sense (yet).
The CQ bit was checked by epertoso@chromium.org
The patchset sent to the CQ was uploaded after l-g-t-m from bmeurer@chromium.org Link to the patchset: https://codereview.chromium.org/1845043004/#ps60001 (title: "Update")
CQ is trying da patch. Follow status at https://chromium-cq-status.appspot.com/patch-status/1845043004/60001 View timeline at https://chromium-cq-status.appspot.com/patch-timeline/1845043004/60001
On 2016/04/01 at 09:20:49, bmeurer wrote: > LGTM once comment addressed. > > https://codereview.chromium.org/1845043004/diff/40001/src/compiler/x64/instru... > File src/compiler/x64/instruction-selector-x64.cc (right): > > https://codereview.chromium.org/1845043004/diff/40001/src/compiler/x64/instru... > src/compiler/x64/instruction-selector-x64.cc:665: default: > No default please, and use UNREACHABLE for cases that don't make sense (yet). Done.
Message was sent while issue was closed.
Committed patchset #4 (id:60001)
Message was sent while issue was closed.
Description was changed from ========== [x64] Optimize loading SMIs. Especially when loading and untagging SMIs within code stubs, instances of the following pattern appear in the generated code: movq %rax,[%rbx+%rcx*4+0xf] sarq %rax, 32 This CL changes that code to: movsxlq %rax, [%ebx+%ecx*4+0x13] BUG= ========== to ========== [x64] Optimize loading SMIs. Especially when loading and untagging SMIs within code stubs, instances of the following pattern appear in the generated code: movq %rax,[%rbx+%rcx*4+0xf] sarq %rax, 32 This CL changes that code to: movsxlq %rax, [%ebx+%ecx*4+0x13] BUG= Committed: https://crrev.com/9ca9195dd4ae363113692347c337f088c998bcd5 Cr-Commit-Position: refs/heads/master@{#35194} ==========
Message was sent while issue was closed.
Patchset 4 (id:??) landed as https://crrev.com/9ca9195dd4ae363113692347c337f088c998bcd5 Cr-Commit-Position: refs/heads/master@{#35194} |
