[x64] Optimize loading SMIs.

src/compiler/x64/instruction-selector-x64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <algorithm>
 
 #include "src/base/adapters.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
@@ skipping 45 matching lines @@
         return rep == MachineRepresentation::kWord16;
       case kX64Cmp8:
       case kX64Test8:
         return rep == MachineRepresentation::kWord8;
       default:
         break;
     }
     return false;
   }
 
+  AddressingMode EnsureHasDisplacement(
+      const BaseWithIndexAndDisplacement64Matcher& matcher,
+      AddressingMode mode) {
+    if (matcher.displacement() != nullptr) {
+      return mode;
+    }
+    DCHECK(mode == kMode_MR || (kMode_MR1 <= mode && mode <= kMode_MR8) ||

[Benedikt Meurer, 2016/04/01 08:33:00]

As discussed offline, please do a switch here. And please inline into the
callsite.

[epertoso, 2016/04/01 09:16:44]

Done.

+           (kMode_M4 == mode || kMode_M8 == mode));
+    return mode == kMode_MR ? kMode_MRI : static_cast<AddressingMode>(mode + 4);
+  }
+
   AddressingMode GenerateMemoryOperandInputs(Node* index, int scale_exponent,
                                              Node* base, Node* displacement,
                                              InstructionOperand inputs[],
                                              size_t* input_count) {
     AddressingMode mode = kMode_MRI;
     if (base != nullptr) {
       inputs[(*input_count)++] = UseRegister(base);
       if (index != nullptr) {
         DCHECK(scale_exponent >= 0 && scale_exponent <= 3);
         inputs[(*input_count)++] = UseRegister(index);
@@ skipping 535 matching lines @@
     } else if (mleft.right().Is(24) && m.right().Is(24)) {
       Emit(kX64Movsxbl, g.DefineAsRegister(node), g.Use(mleft.left().node()));
       return;
     }
   }
   VisitWord32Shift(this, node, kX64Sar32);
 }
 
 
 void InstructionSelector::VisitWord64Sar(Node* node) {
+  X64OperandGenerator g(this);
+  Int64BinopMatcher m(node);
+  if (CanCover(m.node(), m.left().node()) && m.left().IsLoad() &&
+      m.right().Is(32)) {
+    // Just load and sign-extend the interesting 4 bytes instead. This happens,
+    // for example, when we're loading and untagging SMIs.
+    BaseWithIndexAndDisplacement64Matcher mleft(m.left().node(), true);
+    if (mleft.matches() && (mleft.displacement() == nullptr ||
+                            g.CanBeImmediate(mleft.displacement()))) {
+      size_t input_count = 0;
+      InstructionOperand inputs[3];
+      AddressingMode mode = g.GetEffectiveAddressMemoryOperand(
+          m.left().node(), inputs, &input_count);
+      mode = g.EnsureHasDisplacement(mleft, mode);
+      if (mleft.displacement() == nullptr) {
+        inputs[input_count++] = ImmediateOperand(ImmediateOperand::INLINE, 4);
+      } else {
+        ImmediateOperand* op = ImmediateOperand::cast(&inputs[input_count - 1]);
+        int32_t displacement = sequence()->GetImmediate(op).ToInt32();
+        *op = ImmediateOperand(ImmediateOperand::INLINE, displacement + 4);
+      }
+      InstructionOperand outputs[] = {g.DefineAsRegister(node)};
+      InstructionCode code = kX64Movsxlq | AddressingModeField::encode(mode);
+      Emit(code, 1, outputs, input_count, inputs);
+      return;
+    }
+  }
   VisitWord64Shift(this, node, kX64Sar);
 }
 
 
 void InstructionSelector::VisitWord32Ror(Node* node) {
   VisitWord32Shift(this, node, kX64Ror32);
 }
 
 
 void InstructionSelector::VisitWord64Ror(Node* node) {
@@ skipping 1341 matching lines @@
              MachineOperatorBuilder::kFloat64RoundTruncate |
              MachineOperatorBuilder::kFloat32RoundTiesEven |
              MachineOperatorBuilder::kFloat64RoundTiesEven;
   }
   return flags;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8