[turbofan] Implement rounding of floats on x64 and ia32 without sse4.1.

src/x64/disasm-x64.cc

Index: src/x64/disasm-x64.cc
diff --git a/src/x64/disasm-x64.cc b/src/x64/disasm-x64.cc
index 05b199d558df567d3fae301a15a84713d61313d6..5f12c6cde284e52a6e0a50e85f98ab0122ba09d2 100644
--- a/src/x64/disasm-x64.cc
+++ b/src/x64/disasm-x64.cc
@@ -994,6 +994,11 @@ int DisassemblerX64::AVXInstruction(byte* data) {
                        NameOfCPURegister(regop));
         current += PrintRightXMMOperand(current);
         break;
+      case 0x2d:
+        AppendToBuffer("vcvtss2si%s %s,", vex_w() ? "q" : "",
+                       NameOfCPURegister(regop));
+        current += PrintRightXMMOperand(current);
+        break;
       case 0x58:
         AppendToBuffer("vaddss %s,%s,", NameOfXMMRegister(regop),
                        NameOfXMMRegister(vvvv));
@@ -1239,6 +1244,11 @@ int DisassemblerX64::AVXInstruction(byte* data) {
                        NameOfXMMRegister(vvvv));
         current += PrintRightXMMOperand(current);
         break;
+      case 0x56:
+        AppendToBuffer("vorps %s,%s,", NameOfXMMRegister(regop),
+                       NameOfXMMRegister(vvvv));
+        current += PrintRightXMMOperand(current);
+        break;
       case 0x57:
         AppendToBuffer("vxorps %s,%s,", NameOfXMMRegister(regop),
                        NameOfXMMRegister(vvvv));
@@ -1288,6 +1298,12 @@ int DisassemblerX64::AVXInstruction(byte* data) {
                        NameOfXMMRegister(regop));
         current += PrintRightOperand(current);
         break;
+      case 0x72:
+        AppendToBuffer("%s %s,", regop == 6 ? "vpslld" : "vpsrld",
+                       NameOfXMMRegister(vvvv));
+        current += PrintRightXMMOperand(current);
+        AppendToBuffer(",%u", *current++);
+        break;
       case 0x73:
         AppendToBuffer("%s %s,", regop == 6 ? "vpsllq" : "vpsrlq",
                        NameOfXMMRegister(vvvv));
@@ -1711,6 +1727,14 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
       AppendToBuffer("cvttss2si%c %s,",
           operand_size_code(), NameOfCPURegister(regop));
       current += PrintRightXMMOperand(current);
+    } else if (opcode == 0x2D) {
+      // CVTSS2SI:
+      // Convert with rounded scalar single-precision FP to dword integer.
+      int mod, regop, rm;
+      get_modrm(*current, &mod, &regop, &rm);
+      AppendToBuffer("cvtss2si%c %s,", operand_size_code(),
+                     NameOfCPURegister(regop));
+      current += PrintRightXMMOperand(current);
     } else if (opcode == 0x7E) {
       int mod, regop, rm;
       get_modrm(*current, &mod, &regop, &rm);
@@ -1871,6 +1895,27 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
     current += PrintRightOperand(current);
   } else if (opcode == 0x0B) {
     AppendToBuffer("ud2");
+  } else if (opcode == 0xAE) {
+    byte modrm = *(data + 2);
+    int mod, regop, rm;
+    get_modrm(modrm, &mod, &regop, &rm);
+    regop &= 0x7;  // The REX.R bit does not affect the operation.
+    const char* mnem = NULL;
+    switch (regop) {
+      case 2:
+        mnem = "ldmxcsr";
+        break;
+      case 3:
+        mnem = "stmxcsr";
+        break;
+      default:
+        UnimplementedInstruction();
+        return 2;
+    }
+    DCHECK_NOT_NULL(mnem);
+    AppendToBuffer("%s ", mnem);
+    current +=
+        PrintRightOperandHelper(current, &DisassemblerX64::NameOfCPURegister);
   } else {
     UnimplementedInstruction();
   }