Implements include/exclude register lists for translation.

src/IceTargetLoweringARM32.cpp

Index: src/IceTargetLoweringARM32.cpp
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 878f95ec059fbcf5c1e186cd4ff77b8d003cc0ad..7ccbc8718477fa4e956549da7f7c6eab1013288a 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -50,8 +50,8 @@ createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
   return ::Ice::ARM32::TargetHeaderARM32::create(Ctx);
 }
 
-void staticInit(const ::Ice::ClFlags &Flags) {
-  ::Ice::ARM32::TargetARM32::staticInit(Flags);
+void staticInit(::Ice::GlobalContext *Ctx) {
+  ::Ice::ARM32::TargetARM32::staticInit(Ctx);
 }
 } // end of namespace ARM32
 
@@ -229,14 +229,30 @@ constexpr SizeT NumVec128Args =
 #undef X
     ;
 std::array<uint32_t, NumVec128Args> Vec128ArgInitializer;
+
+static IceString RegNameSeparator(", ");
+
 } // end of anonymous namespace
 
+llvm::SmallBitVector TargetARM32::RegisterSetMask(RegARM32::Reg_NUM);
+
 TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(Ctx->getFlags().getUseSandboxing()),
       CPUFeatures(Func->getContext()->getFlags()) {}
 
-void TargetARM32::staticInit(const ClFlags &Flags) {
-  (void)Flags;
+void TargetARM32::staticInit(GlobalContext *Ctx) {
+  RegisterSetMask = getRegisterSetMask(
+      Ctx, RegARM32::Reg_NUM, RegARM32::Num_RegClasses,
+      [](int32_t RegNum) -> SizeT { return RegARM32::getRegClass(RegNum); },
+      [](int32_t RegNum) -> IceString {
+        std::string Name = RegARM32::getRegName(RegNum);
+        for (size_t Pos = Name.find(RegNameSeparator); Pos != std::string::npos;
+             Pos = Name.find(RegNameSeparator)) {
+          Name.replace(Pos, RegNameSeparator.size(), ":");
+        }
+        return Name;
+      });
+
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
@@ -1832,7 +1848,7 @@ llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
 
-  for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
+  for (SizeT i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::Table[i];
     if (Entry.Scratch && (Include & RegSet_CallerSave))
       Registers[i] = true;
@@ -1852,6 +1868,7 @@ llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
       Registers[i] = false;
   }
 
+  Registers &= RegisterSetMask;
   return Registers;
 }