Implements include/exclude register lists for translation.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 32 matching lines @@
 std::unique_ptr<::Ice::TargetDataLowering>
 createTargetDataLowering(::Ice::GlobalContext *Ctx) {
   return ::Ice::ARM32::TargetDataARM32::create(Ctx);
 }
 
 std::unique_ptr<::Ice::TargetHeaderLowering>
 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
   return ::Ice::ARM32::TargetHeaderARM32::create(Ctx);
 }
 
-void staticInit(const ::Ice::ClFlags &Flags) {
-  ::Ice::ARM32::TargetARM32::staticInit(Flags);
+void staticInit(::Ice::GlobalContext *Ctx) {
+  ::Ice::ARM32::TargetARM32::staticInit(Ctx);
 }
 } // end of namespace ARM32
 
 namespace Ice {
 namespace ARM32 {
 
 // Defines the RegARM32::Table table with register information.
 constexpr RegARM32::TableType RegARM32::Table[];
 
 namespace {
@@ skipping 157 matching lines @@
 std::array<uint32_t, NumFP64Args> FP64ArgInitializer;
 
 constexpr SizeT NumVec128Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg > 0)) ? 1 : 0)
     REGARM32_VEC128_TABLE
 #undef X
     ;
 std::array<uint32_t, NumVec128Args> Vec128ArgInitializer;
+
+static IceString RegNameSeparator(", ");
+
 } // end of anonymous namespace
 
+llvm::SmallBitVector TargetARM32::RegisterSetMask(RegARM32::Reg_NUM);
+
 TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(Ctx->getFlags().getUseSandboxing()),
       CPUFeatures(Func->getContext()->getFlags()) {}
 
-void TargetARM32::staticInit(const ClFlags &Flags) {
-  (void)Flags;
+void TargetARM32::staticInit(GlobalContext *Ctx) {
+  RegisterSetMask = getRegisterSetMask(
+      Ctx, RegARM32::Reg_NUM, RegARM32::Num_RegClasses,
+      [](int32_t RegNum) -> SizeT { return RegARM32::getRegClass(RegNum); },
+      [](int32_t RegNum) -> IceString {
+        std::string Name = RegARM32::getRegName(RegNum);
+        for (size_t Pos = Name.find(RegNameSeparator); Pos != std::string::npos;
+             Pos = Name.find(RegNameSeparator)) {
+          Name.replace(Pos, RegNameSeparator.size(), ":");
+        }
+        return Name;
+      });
+
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
   ScratchRegs.resize(RegARM32::Reg_NUM);
   for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::Table[i];
@@ skipping 1575 matching lines @@
     }
   }
   llvm::report_fatal_error("Unsupported operand type");
   return nullptr;
 }
 
 llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
 
-  for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
+  for (SizeT i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::Table[i];
     if (Entry.Scratch && (Include & RegSet_CallerSave))
       Registers[i] = true;
     if (Entry.Preserved && (Include & RegSet_CalleeSave))
       Registers[i] = true;
     if (Entry.StackPtr && (Include & RegSet_StackPointer))
       Registers[i] = true;
     if (Entry.FramePtr && (Include & RegSet_FramePointer))
       Registers[i] = true;
     if (Entry.Scratch && (Exclude & RegSet_CallerSave))
       Registers[i] = false;
     if (Entry.Preserved && (Exclude & RegSet_CalleeSave))
       Registers[i] = false;
     if (Entry.StackPtr && (Exclude & RegSet_StackPointer))
       Registers[i] = false;
     if (Entry.FramePtr && (Exclude & RegSet_FramePointer))
       Registers[i] = false;
   }
 
+  Registers &= RegisterSetMask;
   return Registers;
 }
 
 void TargetARM32::lowerAlloca(const InstAlloca *Inst) {
   // Conservatively require the stack to be aligned. Some stack adjustment
   // operations implemented below assume that the stack is aligned before the
   // alloca. All the alloca code ensures that the stack alignment is preserved
   // after the alloca. The stack alignment restriction can be relaxed in some
   // cases.
   NeedsStackAlignment = true;
@@ skipping 4583 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace ARM32
 } // end of namespace Ice