Implements include/exclude register lists for translation.

src/IceTargetLowering.cpp

Index: src/IceTargetLowering.cpp
diff --git a/src/IceTargetLowering.cpp b/src/IceTargetLowering.cpp
index 04f77e61b2caf26ea4fe4bedffc1efae35434fcd..72a716e748f788e1667d83b8adfd19e436cb7c23 100644
--- a/src/IceTargetLowering.cpp
+++ b/src/IceTargetLowering.cpp
@@ -39,7 +39,7 @@
 //       createTargetDataLowering(Ice::GlobalContext*);
 //   unique_ptr<Ice::TargetHeaderLowering>
 //       createTargetHeaderLowering(Ice::GlobalContext *);
-//   void staticInit(const ::Ice::ClFlags &Flags);
+//   void staticInit(::Ice::GlobalContext *);
 // }
 #define SUBZERO_TARGET(X)                                                      \
   namespace X {                                                                \
@@ -49,7 +49,7 @@
   createTargetDataLowering(::Ice::GlobalContext *Ctx);                         \
   std::unique_ptr<::Ice::TargetHeaderLowering>                                 \
   createTargetHeaderLowering(::Ice::GlobalContext *Ctx);                       \
-  void staticInit(const ::Ice::ClFlags &Flags);                                \
+  void staticInit(::Ice::GlobalContext *Ctx);                                  \
   } // end of namespace X
 #include "llvm/Config/SZTargets.def"
 #undef SUBZERO_TARGET
@@ -116,6 +116,67 @@ Variable *LoweringContext::availabilityGet(Operand *Src) const {
   return nullptr;
 }
 
+llvm::SmallBitVector TargetLowering::getRegisterSetMask(
+    GlobalContext *Ctx, SizeT NumRegs, SizeT NumRegClasses,
+    std::function<SizeT(int32_t)> RegClassFcn,
+    std::function<IceString(int32_t)> RegNameFcn) {
+  llvm::SmallBitVector RegMask(NumRegs);
+
+  // Collect registers to use.
+  const std::unordered_set<std::string> &RegUses =
+      Ctx->getFlags().getUseRestrictedRegisters();
+  std::vector<llvm::SmallBitVector> AllRegClass(NumRegClasses, RegMask);
+  std::vector<llvm::SmallBitVector> UseRegClass(NumRegClasses, RegMask);
+  for (SizeT i = 0; i < NumRegs; ++i) {
+    SizeT ClassIndex = RegClassFcn(i);

[Jim Stichnoth, 2016/01/13 16:24:54]

RegClassFcn is supposed to take an int32_t argument, but i is SizeT.

Maybe types would all work out if i and NumRegs were int32_t?

[Karl, 2016/01/14 18:27:19]

Done.

+    assert(ClassIndex < NumRegClasses);
+    AllRegClass[ClassIndex][i] = true;
+    if (RegUses.count(RegNameFcn(i)))
+      UseRegClass[ClassIndex][i] = true;
+  }
+  for (SizeT ClassIndex = 0; ClassIndex < NumRegClasses; ++ClassIndex) {
+    RegMask |= (UseRegClass[ClassIndex].any() ? UseRegClass[ClassIndex]
+                                              : AllRegClass[ClassIndex]);
+  }
+
+  // Remove registers to exclude.
+  const std::unordered_set<std::string> &RegExcludes =
+      Ctx->getFlags().getExcludedRegisters();
+  for (SizeT i = 0; i < NumRegs; ++i) {
+    if (RegExcludes.count(RegNameFcn(i)))
+      RegMask[i] = false;
+  }
+
+  // Trace registers available if requested.
+  if (BuildDefs::dump() && NumRegs &&
+      (Ctx->getFlags().getVerbose() & IceV_AvailableRegs)) {
+    Ostream &Out = Ctx->getStrEmit();

[Jim Stichnoth, 2016/01/13 16:24:54]

getStrDump()

and usually, the variable is named "Str".
i.e.:
  Ostream &Str = Ctx->getStrDump();

[Karl, 2016/01/14 18:27:19]

Done.

+    Out << "Registers available for register allocation:\n";
+    constexpr SizeT RegistersPerLine = 15;
+    bool AtBeginning = true;
+    SizeT Count = 0;
+    for (SizeT i = 0; i < NumRegs; ++i) {
+      if (!RegMask[i])
+        continue;
+      if (AtBeginning) {
+        Out << "  ";
+        AtBeginning = false;
+      } else {
+        Out << ", ";
+      }
+      if ((Count > 0) && ((Count % RegistersPerLine) == 0)) {
+        Out << "\n  ";
+      }
+      ++Count;
+      Out << RegNameFcn(i);
+    }
+    if (!AtBeginning)
+      Out << "\n";
+  }
+
+  return RegMask;
+}
+
 std::unique_ptr<TargetLowering>
 TargetLowering::createLowering(TargetArch Target, Cfg *Func) {
   switch (Target) {
@@ -129,8 +190,8 @@ TargetLowering::createLowering(TargetArch Target, Cfg *Func) {
   }
 }
 
-void TargetLowering::staticInit(const ClFlags &Flags) {
-  const TargetArch Target = Flags.getTargetArch();
+void TargetLowering::staticInit(GlobalContext *Ctx) {
+  const TargetArch Target = Ctx->getFlags().getTargetArch();
   // Call the specified target's static initializer.
   switch (Target) {
   default:
@@ -142,7 +203,7 @@ void TargetLowering::staticInit(const ClFlags &Flags) {
       return;                                                                  \
     }                                                                          \
     InitGuard##X = true;                                                       \
-    ::X::staticInit(Flags);                                                    \
+    ::X::staticInit(Ctx);                                                      \
   } break;
 #include "llvm/Config/SZTargets.def"
 #undef SUBZERO_TARGET