Subzero. ARM32. Introduces explicit register parameter attribute.

src/IceInstARM32.def

Index: src/IceInstARM32.def
diff --git a/src/IceInstARM32.def b/src/IceInstARM32.def
index 2c06f9708b41ea2f5304f48d22ff94a19ac7991f..79fd47311c8d8f8eaabb50a6ac7e6fd403403acc 100644
--- a/src/IceInstARM32.def
+++ b/src/IceInstARM32.def
@@ -33,25 +33,41 @@
 // script.
 
 #define REGARM32_GPR_TABLE                                                     \
-  /* val, encode, name, scratch,preserved,stackptr,frameptr,                   \
-     isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */                     \
-  X(Reg_r0,   0, "r0",  1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r0r1))          \
-  X(Reg_r1,   1, "r1",  1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r0r1))          \
-  X(Reg_r2,   2, "r2",  1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r2r3))          \
-  X(Reg_r3,   3, "r3",  1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r2r3))          \
-  X(Reg_r4,   4, "r4",  0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r4r5))          \
-  X(Reg_r5,   5, "r5",  0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r4r5))          \
-  X(Reg_r6,   6, "r6",  0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r6r7))          \
-  X(Reg_r7,   7, "r7",  0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r6r7))          \
-  X(Reg_r8,   8, "r8",  0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r8r9))          \
-  X(Reg_r9,   9, "r9",  0,1,0,0, 0,0,0,0,0, REGLIST1(RegARM32, r8r9))          \
-  X(Reg_r10, 10, "r10", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r10fp))         \
-  X(Reg_fp,  11, "fp",  0,1,0,1, 1,0,0,0,0, REGLIST1(RegARM32, r10fp))         \
-  X(Reg_ip,  12, "ip",  1,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, ip))            \
-  X(Reg_sp,  13, "sp",  0,0,1,0, 0,0,0,0,0, REGLIST1(RegARM32, sp))            \
-  X(Reg_lr,  14, "lr",  0,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, lr))            \
-  X(Reg_pc,  15, "pc",  0,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, pc))
-//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
+  /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,        \
+     isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */                 \
+  X(Reg_r0,  0,  "r0",  1, 1, 0, 0, 0, 1, 0, 0, 0, 0,                          \

[Jim Stichnoth, 2015/12/10 19:04:05]

I realize that generation of these tables is now entirely scripted, so take the
following comments as completely optional.

1. If, during development or debugging, I want to look at this table, I really
want to look at this instantiation of it rather than the claimed-source-of-truth
.py file.  As such, I would very much like to try to maintain 80-col.

2. The original table packs somewhat-related columns close together by not using
a space character after a comma.  This makes it easier to visually locate a
column from some row deep in the table.  (It also helps preserve 80-col.)

3. The original table deliberately omits listing trivial self-aliases.  This
makes the table easier to read (IMO) by minimizing basically redundant
information.  (It also helps preserve 80-col.)

4. Many columns are "sparse" in that they contain mostly zeroes.  It might be
more readable (or maybe not) if "0" in such a column is replaced with a single
space character.  Then e.g. "blah = isInt;" in an x-macro is replaced with "blah
= isInt + 0;".

5. It would be really cool if there were a good way to remove the redundant
"RegARM32" from every X() line.  I originally tried but this is the best I could
do.

Regarding #1, maybe the Makefile could invoke the .py file to auto-generate
another .def file to #include here, and completely ignore the legacy 80-col
issue.

[Jim Stichnoth, 2015/12/11 06:17:13]

Actually, I took another look at the .py file, and I see that the sparsity is
already represented there.  Cool!
If you do this (and after more consideration I think you should), I would make
the auto-generated .def file be officially checked into the repo (as opposed to
being added to .gitignore).  That way you don't have to figure out how to modify
the Makefile to auto-gen the .def file as needed.

[John, 2015/12/11 15:43:29]

I added the other .def file. In the future I will #include it where it is needed
-- .def #include another .def is confusing.

+    REGLIST2(RegARM32, r0, r0r1))                                              \
+  X(Reg_r1,  1,  "r1",  2, 1, 0, 0, 0, 1, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, r1, r0r1))                                              \
+  X(Reg_r2,  2,  "r2",  3, 1, 0, 0, 0, 1, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, r2, r2r3))                                              \
+  X(Reg_r3,  3,  "r3",  4, 1, 0, 0, 0, 1, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, r3, r2r3))                                              \
+  X(Reg_r4,  4,  "r4",  0, 0, 1, 0, 0, 1, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, r4, r4r5))                                              \
+  X(Reg_r5,  5,  "r5",  0, 0, 1, 0, 0, 1, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, r5, r4r5))                                              \
+  X(Reg_r6,  6,  "r6",  0, 0, 1, 0, 0, 1, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, r6, r6r7))                                              \
+  X(Reg_r7,  7,  "r7",  0, 0, 1, 0, 0, 1, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, r7, r6r7))                                              \
+  X(Reg_r8,  8,  "r8",  0, 0, 1, 0, 0, 1, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, r8, r8r9))                                              \
+  X(Reg_r9,  9,  "r9",  0, 0, 1, 0, 0, 0, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, r9, r8r9))                                              \
+  X(Reg_r10, 10, "r10", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, r10, r10fp))                                            \
+  X(Reg_fp,  11,  "fp", 0, 0, 1, 0, 1, 1, 0, 0, 0, 0,                          \
+    REGLIST2(RegARM32, fp, r10fp))                                             \
+  X(Reg_ip,  12,  "ip", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,                          \
+    REGLIST1(RegARM32, ip))                                                    \
+  X(Reg_sp,  13,  "sp", 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,                          \
+    REGLIST1(RegARM32, sp))                                                    \
+  X(Reg_lr,  14,  "lr", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                          \
+    REGLIST1(RegARM32, lr))                                                    \
+  X(Reg_pc,  15,  "pc", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                          \
+    REGLIST1(RegARM32, pc))
+//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 
 // The following defines a table with the available pairs of consecutive i32
@@ -60,54 +76,92 @@
 // is preserved, then we mark the whole pair as preserved to help the register
 // allocator.
 #define REGARM32_I64PAIR_TABLE                                                 \
-  /* val, encode, name, scratch,preserved,stackptr,frameptr,                   \
-     isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */                     \
-  X(Reg_r0r1,   0, "r0, r1",  1,0,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r0, r1))  \
-  X(Reg_r2r3,   2, "r2, r3",  1,0,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r2, r3))  \
-  X(Reg_r4r5,   4, "r4, r5",  0,1,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r4, r5))  \
-  X(Reg_r6r7,   6, "r6, r7",  0,1,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r6, r7))  \
-  X(Reg_r8r9,   8, "r8, r9",  0,1,0,0, 0,0,0,0,0, REGLIST2(RegARM32, r8, r9))  \
-  X(Reg_r10fp, 10, "r10, fp", 0,1,0,0, 0,0,0,0,0, REGLIST2(RegARM32, r10, fp))
-//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
+  /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,        \
+     isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */                 \
+  X(Reg_r0r1,   0,  "r0, r1", 1, 1, 0, 0, 0, 0, 1, 0, 0, 0,                    \
+    REGLIST3(RegARM32, r0r1, r0, r1))                                          \
+  X(Reg_r2r3,   2,  "r2, r3", 2, 1, 0, 0, 0, 0, 1, 0, 0, 0,                    \
+    REGLIST3(RegARM32, r2r3, r2, r3))                                          \
+  X(Reg_r4r5,   4,  "r4, r5", 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,                    \
+    REGLIST3(RegARM32, r4r5, r4, r5))                                          \
+  X(Reg_r6r7,   6,  "r6, r7", 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,                    \
+    REGLIST3(RegARM32, r6r7, r6, r7))                                          \
+  X(Reg_r8r9,   8,  "r8, r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,                    \
+    REGLIST3(RegARM32, r8r9, r8, r9))                                          \
+  X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,                    \
+    REGLIST3(RegARM32, r10fp, r10, fp))
+//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 
 // S registers 0-15 are scratch, but 16-31 are preserved.
 #define REGARM32_FP32_TABLE                                                    \
-  /* val, encode, name, scratch,preserved,stackptr,frameptr,                   \
-     isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */                     \
-  X(Reg_s0,   0, "s0",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d0, q0))       \
-  X(Reg_s1,   1, "s1",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d0, q0))       \
-  X(Reg_s2,   2, "s2",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d1, q0))       \
-  X(Reg_s3,   3, "s3",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d1, q0))       \
-  X(Reg_s4,   4, "s4",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d2, q1))       \
-  X(Reg_s5,   5, "s5",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d2, q1))       \
-  X(Reg_s6,   6, "s6",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d3, q1))       \
-  X(Reg_s7,   7, "s7",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d3, q1))       \
-  X(Reg_s8,   8, "s8",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d4, q2))       \
-  X(Reg_s9,   9, "s9",  1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d4, q2))       \
-  X(Reg_s10, 10, "s10", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d5, q2))       \
-  X(Reg_s11, 11, "s11", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d5, q2))       \
-  X(Reg_s12, 12, "s12", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d6, q3))       \
-  X(Reg_s13, 13, "s13", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d6, q3))       \
-  X(Reg_s14, 14, "s14", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d7, q3))       \
-  X(Reg_s15, 15, "s15", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d7, q3))       \
-  X(Reg_s16, 16, "s16", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d8, q4))       \
-  X(Reg_s17, 17, "s17", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d8, q4))       \
-  X(Reg_s18, 18, "s18", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d9, q4))       \
-  X(Reg_s19, 19, "s19", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32,  d9, q4))       \
-  X(Reg_s20, 20, "s20", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d10, q5))       \
-  X(Reg_s21, 21, "s21", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d10, q5))       \
-  X(Reg_s22, 22, "s22", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d11, q5))       \
-  X(Reg_s23, 23, "s23", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d11, q5))       \
-  X(Reg_s24, 24, "s24", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d12, q6))       \
-  X(Reg_s25, 25, "s25", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d12, q6))       \
-  X(Reg_s26, 26, "s26", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d13, q6))       \
-  X(Reg_s27, 27, "s27", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d13, q6))       \
-  X(Reg_s28, 28, "s28", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d14, q7))       \
-  X(Reg_s29, 29, "s29", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d14, q7))       \
-  X(Reg_s30, 30, "s30", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d15, q7))       \
-  X(Reg_s31, 31, "s31", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d15, q7))
-//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
+  /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,        \
+     isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */                 \
+  X(Reg_s0, 0, "s0", 1, 1, 0, 0, 0, 0, 0, 1, 0, 0,                             \
+    REGLIST3(RegARM32, s0, d0, q0))                                            \
+  X(Reg_s1, 1, "s1", 2, 1, 0, 0, 0, 0, 0, 1, 0, 0,                             \
+    REGLIST3(RegARM32, s1, d0, q0))                                            \
+  X(Reg_s2, 2, "s2", 3, 1, 0, 0, 0, 0, 0, 1, 0, 0,                             \
+    REGLIST3(RegARM32, s2, d1, q0))                                            \
+  X(Reg_s3, 3, "s3", 4, 1, 0, 0, 0, 0, 0, 1, 0, 0,                             \
+    REGLIST3(RegARM32, s3, d1, q0))                                            \
+  X(Reg_s4, 4, "s4", 5, 1, 0, 0, 0, 0, 0, 1, 0, 0,                             \
+    REGLIST3(RegARM32, s4, d2, q1))                                            \
+  X(Reg_s5, 5, "s5", 6, 1, 0, 0, 0, 0, 0, 1, 0, 0,                             \
+    REGLIST3(RegARM32, s5, d2, q1))                                            \
+  X(Reg_s6, 6, "s6", 7, 1, 0, 0, 0, 0, 0, 1, 0, 0,                             \
+    REGLIST3(RegARM32, s6, d3, q1))                                            \
+  X(Reg_s7, 7, "s7", 8, 1, 0, 0, 0, 0, 0, 1, 0, 0,                             \
+    REGLIST3(RegARM32, s7, d3, q1))                                            \
+  X(Reg_s8, 8, "s8", 9, 1, 0, 0, 0, 0, 0, 1, 0, 0,                             \
+    REGLIST3(RegARM32, s8, d4, q2))                                            \
+  X(Reg_s9, 9, "s9", 10, 1, 0, 0, 0, 0, 0, 1, 0, 0,                            \
+    REGLIST3(RegARM32, s9, d4, q2))                                            \
+  X(Reg_s10, 10, "s10", 11, 1, 0, 0, 0, 0, 0, 1, 0, 0,                         \
+    REGLIST3(RegARM32, s10, d5, q2))                                           \
+  X(Reg_s11, 11, "s11", 12, 1, 0, 0, 0, 0, 0, 1, 0, 0,                         \
+    REGLIST3(RegARM32, s11, d5, q2))                                           \
+  X(Reg_s12, 12, "s12", 13, 1, 0, 0, 0, 0, 0, 1, 0, 0,                         \
+    REGLIST3(RegARM32, s12, d6, q3))                                           \
+  X(Reg_s13, 13, "s13", 14, 1, 0, 0, 0, 0, 0, 1, 0, 0,                         \
+    REGLIST3(RegARM32, s13, d6, q3))                                           \
+  X(Reg_s14, 14, "s14", 15, 1, 0, 0, 0, 0, 0, 1, 0, 0,                         \
+    REGLIST3(RegARM32, s14, d7, q3))                                           \
+  X(Reg_s15, 15, "s15", 16, 1, 0, 0, 0, 0, 0, 1, 0, 0,                         \
+    REGLIST3(RegARM32, s15, d7, q3))                                           \
+  X(Reg_s16, 16, "s16", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s16, d8, q4))                                           \
+  X(Reg_s17, 17, "s17", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s17, d8, q4))                                           \
+  X(Reg_s18, 18, "s18", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s18, d9, q4))                                           \
+  X(Reg_s19, 19, "s19", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s19, d9, q4))                                           \
+  X(Reg_s20, 20, "s20", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s20, d10, q5))                                          \
+  X(Reg_s21, 21, "s21", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s21, d10, q5))                                          \
+  X(Reg_s22, 22, "s22", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s22, d11, q5))                                          \
+  X(Reg_s23, 23, "s23", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s23, d11, q5))                                          \
+  X(Reg_s24, 24, "s24", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s24, d12, q6))                                          \
+  X(Reg_s25, 25, "s25", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s25, d12, q6))                                          \
+  X(Reg_s26, 26, "s26", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s26, d13, q6))                                          \
+  X(Reg_s27, 27, "s27", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s27, d13, q6))                                          \
+  X(Reg_s28, 28, "s28", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s28, d14, q7))                                          \
+  X(Reg_s29, 29, "s29", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s29, d14, q7))                                          \
+  X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s30, d15, q7))                                          \
+  X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0,                          \
+    REGLIST3(RegARM32, s31, d14, q7))
+//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32,isFP64, isVec128, alias_init)
 
 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch
@@ -117,82 +171,114 @@
 // cause double allocation to bias towards allocating "high" D registers, which
 // do not alias any S registers.
 #define REGARM32_FP64_TABLE                                                    \
-  /* val, encode, name, scratch,preserved,stackptr,frameptr,                   \
-     isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */                     \
-  X(Reg_d31, 31, "d31", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q15))           \
-  X(Reg_d30, 30, "d30", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q15))           \
-  X(Reg_d29, 29, "d29", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q14))           \
-  X(Reg_d28, 28, "d28", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q14))           \
-  X(Reg_d27, 27, "d27", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q13))           \
-  X(Reg_d26, 26, "d26", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q13))           \
-  X(Reg_d25, 25, "d25", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q12))           \
-  X(Reg_d24, 24, "d24", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q12))           \
-  X(Reg_d23, 23, "d23", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q11))           \
-  X(Reg_d22, 22, "d22", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q11))           \
-  X(Reg_d21, 21, "d21", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q10))           \
-  X(Reg_d20, 20, "d20", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q10))           \
-  X(Reg_d19, 19, "d19", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q9))            \
-  X(Reg_d18, 18, "d18", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q9))            \
-  X(Reg_d17, 17, "d17", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q8))            \
-  X(Reg_d16, 16, "d16", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q8))            \
-  X(Reg_d15, 15, "d15", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s30, s31, q7))  \
-  X(Reg_d14, 14, "d14", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s28, s29, q7))  \
-  X(Reg_d13, 13, "d13", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s26, s27, q6))  \
-  X(Reg_d12, 12, "d12", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s24, s25, q6))  \
-  X(Reg_d11, 11, "d11", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s22, s23, q5))  \
-  X(Reg_d10, 10, "d10", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s20, s21, q5))  \
-  X(Reg_d9,   9, "d9",  0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s18, s19, q4))  \
-  X(Reg_d8,   8, "d8",  0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s16, s17, q4))  \
-  X(Reg_d7,   7, "d7",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s14, s15, q3))  \
-  X(Reg_d6,   6, "d6",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s12, s13, q3))  \
-  X(Reg_d5,   5, "d5",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s10, s11, q2))  \
-  X(Reg_d4,   4, "d4",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s8, s9, q2))    \
-  X(Reg_d3,   3, "d3",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s6, s7, q1))    \
-  X(Reg_d2,   2, "d2",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s4, s5, q1))    \
-  X(Reg_d1,   1, "d1",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s2, s3, q0))    \
-  X(Reg_d0,   0, "d0",  1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s0, s1, q0))
-//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
+  /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,        \
+     isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */                 \
+  X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d31, q15))                                              \
+  X(Reg_d30, 30, "d30", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d30, q15))                                              \
+  X(Reg_d29, 29, "d29", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d29, q14))                                              \
+  X(Reg_d28, 28, "d28", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d28, q14))                                              \
+  X(Reg_d27, 27, "d27", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d27, q13))                                              \
+  X(Reg_d26, 26, "d26", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d26, q13))                                              \
+  X(Reg_d25, 25, "d25", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d25, q12))                                              \
+  X(Reg_d24, 24, "d24", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d24, q12))                                              \
+  X(Reg_d23, 23, "d23", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d23, q11))                                              \
+  X(Reg_d22, 22, "d22", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d22, q11))                                              \
+  X(Reg_d21, 21, "d21", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d21, q10))                                              \
+  X(Reg_d20, 20, "d20", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d20, q10))                                              \
+  X(Reg_d19, 19, "d19", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d19, q9))                                               \
+  X(Reg_d18, 18, "d18", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d18, q9))                                               \
+  X(Reg_d17, 17, "d17", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d17, q8))                                               \
+  X(Reg_d16, 16, "d16", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST2(RegARM32, d16, q8))                                               \
+  X(Reg_d15, 15, "d15", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST4(RegARM32, d15, q7, s30, s31))                                     \
+  X(Reg_d14, 14, "d14", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST4(RegARM32, d14, q7, s28, s28))                                     \
+  X(Reg_d13, 13, "d13", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST4(RegARM32, d13, q6, s26, s27))                                     \
+  X(Reg_d12, 12, "d12", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST4(RegARM32, d12, q6, s24, s25))                                     \
+  X(Reg_d11, 11, "d11", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST4(RegARM32, d11, q5, s22, s24))                                     \
+  X(Reg_d10, 10, "d10", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0,                          \
+    REGLIST4(RegARM32, d10, q5, s20, s21))                                     \
+  X(Reg_d9, 9, "d9", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0,                             \
+    REGLIST4(RegARM32, d9, q4, s18, s19))                                      \
+  X(Reg_d8, 8, "d8", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0,                             \
+    REGLIST4(RegARM32, d8, q4, s16, s17))                                      \
+  X(Reg_d7, 7, "d7", 8, 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
+    REGLIST4(RegARM32, d7, q3, s14, s15))                                      \
+  X(Reg_d6, 6, "d6", 7, 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
+    REGLIST4(RegARM32, d6, q3, s12, s13))                                      \
+  X(Reg_d5, 5, "d5", 6, 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
+    REGLIST4(RegARM32, d5, q2, s10, s11))                                      \
+  X(Reg_d4, 4, "d4", 5, 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
+    REGLIST4(RegARM32, d4, q2, s8, s9))                                        \
+  X(Reg_d3, 3, "d3", 4, 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
+    REGLIST4(RegARM32, d3, q1, s6, s7))                                        \
+  X(Reg_d2, 2, "d2", 3, 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
+    REGLIST4(RegARM32, d2, q1, s4, s5))                                        \
+  X(Reg_d1, 1, "d1", 2, 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
+    REGLIST4(RegARM32, d1, q0, s2, s3))                                        \
+  X(Reg_d0, 0, "d0", 1, 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
+    REGLIST4(RegARM32, d0, q0, s0, s1))
+//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 
 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch
 // (if supported by the D32 feature). Q registers are defined in reverse order
 // for the same reason as D registers.
 #define REGARM32_VEC128_TABLE                                                  \
-  /* val, encode, name, scratch, preserved, stackptr, frameptr,                \
+  /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,        \
      isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */                 \
-  X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
-    REGLIST2(RegARM32, d30, d31))                                              \
-  X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
-    REGLIST2(RegARM32, d28, d29))                                              \
-  X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
-    REGLIST2(RegARM32, d26, d27))                                              \
-  X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
-    REGLIST2(RegARM32, d24, d25))                                              \
-  X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
-    REGLIST2(RegARM32, d22, d23))                                              \
-  X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
-    REGLIST2(RegARM32, d20, d21))                                              \
-  X(Reg_q9, 9, "q9", 1, 0, 0, 0, 0, 0, 0, 0, 1,                                \
-    REGLIST2(RegARM32, d18, d19))                                              \
-  X(Reg_q8, 8, "q8", 1, 0, 0, 0, 0, 0, 0, 0, 1,                                \
-    REGLIST2(RegARM32, d16, d17))                                              \
-  X(Reg_q7, 7, "q7", 0, 1, 0, 0, 0, 0, 0, 0, 1,                                \
-    REGLIST6(RegARM32, s28, s29, s30, s31, d14, d15))                          \
-  X(Reg_q6, 6, "q6", 0, 1, 0, 0, 0, 0, 0, 0, 1,                                \
-    REGLIST6(RegARM32, s24, s25, s26, s27, d12, d13))                          \
-  X(Reg_q5, 5, "q5", 0, 1, 0, 0, 0, 0, 0, 0, 1,                                \
-    REGLIST6(RegARM32, s20, s21, s22, s23, d10, d11))                          \
-  X(Reg_q4, 4, "q4", 0, 1, 0, 0, 0, 0, 0, 0, 1,                                \
-    REGLIST6(RegARM32, s16, s17, s18, s19, d8, d9))                            \
-  X(Reg_q3, 3, "q3", 1, 0, 0, 0, 0, 0, 0, 0, 1,                                \
-    REGLIST6(RegARM32, s12, s13, s14, s15, d6, d7))                            \
-  X(Reg_q2, 2, "q2", 1, 0, 0, 0, 0, 0, 0, 0, 1,                                \
-    REGLIST6(RegARM32, s8, s9, s10, s11, d4, d5))                              \
-  X(Reg_q1, 1, "q1", 1, 0, 0, 0, 0, 0, 0, 0, 1,                                \
-    REGLIST6(RegARM32, s4, s5, s6, s7, d2, d3))                                \
-  X(Reg_q0, 0, "q0", 1, 0, 0, 0, 0, 0, 0, 0, 1,                                \
-    REGLIST6(RegARM32, s0, s1, s2, s3, d0, d1))
-//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
+  X(Reg_q15, 15, "q15", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1,                          \
+    REGLIST3(RegARM32, q15, d30, d31))                                         \
+  X(Reg_q14, 14, "q14", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1,                          \
+    REGLIST3(RegARM32, q14, d28, d29))                                         \
+  X(Reg_q13, 13, "q13", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1,                          \
+    REGLIST3(RegARM32, q13, d26, d27))                                         \
+  X(Reg_q12, 12, "q12", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1,                          \
+    REGLIST3(RegARM32, q12, d24, d25))                                         \
+  X(Reg_q11, 11, "q11", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1,                          \
+    REGLIST3(RegARM32, q11, d22, d23))                                         \
+  X(Reg_q10, 10, "q10", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1,                          \
+    REGLIST3(RegARM32, q10, d20, d21))                                         \
+  X(Reg_q9, 9, "q9", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
+    REGLIST3(RegARM32, q9, d18, d19))                                          \
+  X(Reg_q8, 8, "q8", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
+    REGLIST3(RegARM32, q8, d16, d17))                                          \
+  X(Reg_q7, 7, "q7", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1,                             \
+    REGLIST7(RegARM32, q7, d14, d15, s28, s29, s30, s31))                      \
+  X(Reg_q6, 6, "q6", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1,                             \
+    REGLIST7(RegARM32, q6, d12, d13, s24, s25, s26, s27))                      \
+  X(Reg_q5, 5, "q5", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1,                             \
+    REGLIST7(RegARM32, q5, d10, d11, s20, s21, s22, s23))                      \
+  X(Reg_q4, 4, "q4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1,                             \
+    REGLIST7(RegARM32, q4, d8, d9, s16, s17, s18, s19))                        \
+  X(Reg_q3, 3, "q3", 4, 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
+    REGLIST7(RegARM32, q3, d6, d7, s12, s13, s14, s15))                        \
+  X(Reg_q2, 2, "q2", 3, 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
+    REGLIST7(RegARM32, q2, d4, d5, s8, s9, s10, s11))                          \
+  X(Reg_q1, 1, "q1", 2, 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
+    REGLIST7(RegARM32, q1, d2, d3, s4, s5, s6, s7))                            \
+  X(Reg_q0, 0, "q0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 1,                             \
+    REGLIST7(RegARM32, q0, d0, d1, s0, s1, s2, s3))
+//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 
 // We also provide a combined table, so that there is a namespace where all of
@@ -200,14 +286,14 @@
 // contrast to the above, where the "encode" is based on how the register
 // numbers will be encoded in binaries and values can overlap.
 #define REGARM32_TABLE                                                         \
-  /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt,         \
-     isFP32, isFP64, isVec128, alias_init */                                   \
+  /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,        \
+     isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */                 \
   REGARM32_GPR_TABLE                                                           \
   REGARM32_I64PAIR_TABLE                                                       \
   REGARM32_FP32_TABLE                                                          \
   REGARM32_FP64_TABLE                                                          \
   REGARM32_VEC128_TABLE
-//#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
+//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
 //          isInt, isFP32, isFP64, isVec128, alias_init)
 
 #define REGARM32_TABLE_BOUNDS                                                  \