src/IceInstARM32.def - Issue 1508423003: Subzero. ARM32. Introduces explicit register parameter attribute.

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Issue 1508423003: Subzero. ARM32. Introduces explicit register parameter attribute. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Adds some comments; make format; make presubmit Created 5 years ago

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1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --- C++ --===//	1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --- C++ --===//

2 //	2 //

3 // The Subzero Code Generator	3 // The Subzero Code Generator

4 //	4 //

5 // This file is distributed under the University of Illinois Open Source	5 // This file is distributed under the University of Illinois Open Source

6 // License. See LICENSE.TXT for details.	6 // License. See LICENSE.TXT for details.

7 //	7 //

8 //===----------------------------------------------------------------------===//	8 //===----------------------------------------------------------------------===//

9 //	9 //

10 // This file defines properties of ARM32 instructions in the form of x-macros.	10 // This file defines properties of ARM32 instructions in the form of x-macros.

(...skipping 15 matching lines...) Expand all Loading...
26 // register is useful for expanding instructions post-register allocation.	26 // register is useful for expanding instructions post-register allocation.

27 //	27 //

28 // LR is not considered isInt to avoid being allocated as a register. It is	28 // LR is not considered isInt to avoid being allocated as a register. It is

29 // technically preserved, but save/restore is handled separately, based on	29 // technically preserved, but save/restore is handled separately, based on

30 // whether or not the function MaybeLeafFunc.	30 // whether or not the function MaybeLeafFunc.

31 //	31 //

32 // The register tables can be generated using the gen_arm32_reg_tables.py	32 // The register tables can be generated using the gen_arm32_reg_tables.py

33 // script.	33 // script.

34	34

35 #define REGARM32_GPR_TABLE \	35 #define REGARM32_GPR_TABLE \

36 /* val, encode, name, scratch,preserved,stackptr,frameptr, \	36 /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \

37 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \	37 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \

38 X(Reg_r0, 0, "r0", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r0r1)) \	38 X(Reg_r0, 0, "r0", 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, \
	Jim Stichnoth 2015/12/10 19:04:05 I realize that generation of these tables is now e I realize that generation of these tables is now entirely scripted, so take the following comments as completely optional. 1. If, during development or debugging, I want to look at this table, I really want to look at this instantiation of it rather than the claimed-source-of-truth .py file. As such, I would very much like to try to maintain 80-col. 2. The original table packs somewhat-related columns close together by not using a space character after a comma. This makes it easier to visually locate a column from some row deep in the table. (It also helps preserve 80-col.) 3. The original table deliberately omits listing trivial self-aliases. This makes the table easier to read (IMO) by minimizing basically redundant information. (It also helps preserve 80-col.) 4. Many columns are "sparse" in that they contain mostly zeroes. It might be more readable (or maybe not) if "0" in such a column is replaced with a single space character. Then e.g. "blah = isInt;" in an x-macro is replaced with "blah = isInt + 0;". 5. It would be really cool if there were a good way to remove the redundant "RegARM32" from every X() line. I originally tried but this is the best I could do. Regarding #1, maybe the Makefile could invoke the .py file to auto-generate another .def file to #include here, and completely ignore the legacy 80-col issue. Jim Stichnoth 2015/12/11 06:17:13 Actually, I took another look at the .py file, and Show quoted text On 2015/12/10 19:04:05, stichnot wrote: > 4. Many columns are "sparse" in that they contain mostly zeroes. It might be > more readable (or maybe not) if "0" in such a column is replaced with a single > space character. Then e.g. "blah = isInt;" in an x-macro is replaced with "blah > = isInt + 0;". Actually, I took another look at the .py file, and I see that the sparsity is already represented there. Cool! Show quoted text > Regarding #1, maybe the Makefile could invoke the .py file to auto-generate > another .def file to #include here, and completely ignore the legacy 80-col > issue. If you do this (and after more consideration I think you should), I would make the auto-generated .def file be officially checked into the repo (as opposed to being added to .gitignore). That way you don't have to figure out how to modify the Makefile to auto-gen the .def file as needed. John 2015/12/11 15:43:29 I added the other .def file. In the future I will I added the other .def file. In the future I will #include it where it is needed -- .def #include another .def is confusing.
39 X(Reg_r1, 1, "r1", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r0r1)) \	39 REGLIST2(RegARM32, r0, r0r1)) \

40 X(Reg_r2, 2, "r2", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r2r3)) \	40 X(Reg_r1, 1, "r1", 2, 1, 0, 0, 0, 1, 0, 0, 0, 0, \

41 X(Reg_r3, 3, "r3", 1,0,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r2r3)) \	41 REGLIST2(RegARM32, r1, r0r1)) \

42 X(Reg_r4, 4, "r4", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r4r5)) \	42 X(Reg_r2, 2, "r2", 3, 1, 0, 0, 0, 1, 0, 0, 0, 0, \

43 X(Reg_r5, 5, "r5", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r4r5)) \	43 REGLIST2(RegARM32, r2, r2r3)) \

44 X(Reg_r6, 6, "r6", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r6r7)) \	44 X(Reg_r3, 3, "r3", 4, 1, 0, 0, 0, 1, 0, 0, 0, 0, \

45 X(Reg_r7, 7, "r7", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r6r7)) \	45 REGLIST2(RegARM32, r3, r2r3)) \

46 X(Reg_r8, 8, "r8", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r8r9)) \	46 X(Reg_r4, 4, "r4", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \

47 X(Reg_r9, 9, "r9", 0,1,0,0, 0,0,0,0,0, REGLIST1(RegARM32, r8r9)) \	47 REGLIST2(RegARM32, r4, r4r5)) \

48 X(Reg_r10, 10, "r10", 0,1,0,0, 1,0,0,0,0, REGLIST1(RegARM32, r10fp)) \	48 X(Reg_r5, 5, "r5", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \

49 X(Reg_fp, 11, "fp", 0,1,0,1, 1,0,0,0,0, REGLIST1(RegARM32, r10fp)) \	49 REGLIST2(RegARM32, r5, r4r5)) \

50 X(Reg_ip, 12, "ip", 1,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, ip)) \	50 X(Reg_r6, 6, "r6", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \

51 X(Reg_sp, 13, "sp", 0,0,1,0, 0,0,0,0,0, REGLIST1(RegARM32, sp)) \	51 REGLIST2(RegARM32, r6, r6r7)) \

52 X(Reg_lr, 14, "lr", 0,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, lr)) \	52 X(Reg_r7, 7, "r7", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \

53 X(Reg_pc, 15, "pc", 0,0,0,0, 0,0,0,0,0, REGLIST1(RegARM32, pc))	53 REGLIST2(RegARM32, r7, r6r7)) \

54 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,	54 X(Reg_r8, 8, "r8", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \

	55 REGLIST2(RegARM32, r8, r8r9)) \

	56 X(Reg_r9, 9, "r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \

	57 REGLIST2(RegARM32, r9, r8r9)) \

	58 X(Reg_r10, 10, "r10", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \

	59 REGLIST2(RegARM32, r10, r10fp)) \

	60 X(Reg_fp, 11, "fp", 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, \

	61 REGLIST2(RegARM32, fp, r10fp)) \

	62 X(Reg_ip, 12, "ip", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \

	63 REGLIST1(RegARM32, ip)) \

	64 X(Reg_sp, 13, "sp", 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \

	65 REGLIST1(RegARM32, sp)) \

	66 X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

	67 REGLIST1(RegARM32, lr)) \

	68 X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

	69 REGLIST1(RegARM32, pc))

	70 //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,

55 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)	71 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)

56	72

57 // The following defines a table with the available pairs of consecutive i32	73 // The following defines a table with the available pairs of consecutive i32

58 // GPRs starting at an even GPR that is not r14. Those are used to hold i64	74 // GPRs starting at an even GPR that is not r14. Those are used to hold i64

59 // variables for atomic memory operations. If one of the registers in the pair	75 // variables for atomic memory operations. If one of the registers in the pair

60 // is preserved, then we mark the whole pair as preserved to help the register	76 // is preserved, then we mark the whole pair as preserved to help the register

61 // allocator.	77 // allocator.

62 #define REGARM32_I64PAIR_TABLE \	78 #define REGARM32_I64PAIR_TABLE \

63 /* val, encode, name, scratch,preserved,stackptr,frameptr, \	79 /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \

64 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \	80 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \

65 X(Reg_r0r1, 0, "r0, r1", 1,0,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r0, r1)) \	81 X(Reg_r0r1, 0, "r0, r1", 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, \

66 X(Reg_r2r3, 2, "r2, r3", 1,0,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r2, r3)) \	82 REGLIST3(RegARM32, r0r1, r0, r1)) \

67 X(Reg_r4r5, 4, "r4, r5", 0,1,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r4, r5)) \	83 X(Reg_r2r3, 2, "r2, r3", 2, 1, 0, 0, 0, 0, 1, 0, 0, 0, \

68 X(Reg_r6r7, 6, "r6, r7", 0,1,0,0, 0,1,0,0,0, REGLIST2(RegARM32, r6, r7)) \	84 REGLIST3(RegARM32, r2r3, r2, r3)) \

69 X(Reg_r8r9, 8, "r8, r9", 0,1,0,0, 0,0,0,0,0, REGLIST2(RegARM32, r8, r9)) \	85 X(Reg_r4r5, 4, "r4, r5", 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, \

70 X(Reg_r10fp, 10, "r10, fp", 0,1,0,0, 0,0,0,0,0, REGLIST2(RegARM32, r10, fp))	86 REGLIST3(RegARM32, r4r5, r4, r5)) \

71 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,	87 X(Reg_r6r7, 6, "r6, r7", 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, \

	88 REGLIST3(RegARM32, r6r7, r6, r7)) \

	89 X(Reg_r8r9, 8, "r8, r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \

	90 REGLIST3(RegARM32, r8r9, r8, r9)) \

	91 X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \

	92 REGLIST3(RegARM32, r10fp, r10, fp))

	93 //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,

72 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)	94 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)

73	95

74 // S registers 0-15 are scratch, but 16-31 are preserved.	96 // S registers 0-15 are scratch, but 16-31 are preserved.

75 #define REGARM32_FP32_TABLE \	97 #define REGARM32_FP32_TABLE \

76 /* val, encode, name, scratch,preserved,stackptr,frameptr, \	98 /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \

77 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \	99 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \

78 X(Reg_s0, 0, "s0", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d0, q0)) \	100 X(Reg_s0, 0, "s0", 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

79 X(Reg_s1, 1, "s1", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d0, q0)) \	101 REGLIST3(RegARM32, s0, d0, q0)) \

80 X(Reg_s2, 2, "s2", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d1, q0)) \	102 X(Reg_s1, 1, "s1", 2, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

81 X(Reg_s3, 3, "s3", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d1, q0)) \	103 REGLIST3(RegARM32, s1, d0, q0)) \

82 X(Reg_s4, 4, "s4", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d2, q1)) \	104 X(Reg_s2, 2, "s2", 3, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

83 X(Reg_s5, 5, "s5", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d2, q1)) \	105 REGLIST3(RegARM32, s2, d1, q0)) \

84 X(Reg_s6, 6, "s6", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d3, q1)) \	106 X(Reg_s3, 3, "s3", 4, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

85 X(Reg_s7, 7, "s7", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d3, q1)) \	107 REGLIST3(RegARM32, s3, d1, q0)) \

86 X(Reg_s8, 8, "s8", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d4, q2)) \	108 X(Reg_s4, 4, "s4", 5, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

87 X(Reg_s9, 9, "s9", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d4, q2)) \	109 REGLIST3(RegARM32, s4, d2, q1)) \

88 X(Reg_s10, 10, "s10", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d5, q2)) \	110 X(Reg_s5, 5, "s5", 6, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

89 X(Reg_s11, 11, "s11", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d5, q2)) \	111 REGLIST3(RegARM32, s5, d2, q1)) \

90 X(Reg_s12, 12, "s12", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d6, q3)) \	112 X(Reg_s6, 6, "s6", 7, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

91 X(Reg_s13, 13, "s13", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d6, q3)) \	113 REGLIST3(RegARM32, s6, d3, q1)) \

92 X(Reg_s14, 14, "s14", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d7, q3)) \	114 X(Reg_s7, 7, "s7", 8, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

93 X(Reg_s15, 15, "s15", 1,0,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d7, q3)) \	115 REGLIST3(RegARM32, s7, d3, q1)) \

94 X(Reg_s16, 16, "s16", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d8, q4)) \	116 X(Reg_s8, 8, "s8", 9, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

95 X(Reg_s17, 17, "s17", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d8, q4)) \	117 REGLIST3(RegARM32, s8, d4, q2)) \

96 X(Reg_s18, 18, "s18", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d9, q4)) \	118 X(Reg_s9, 9, "s9", 10, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

97 X(Reg_s19, 19, "s19", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d9, q4)) \	119 REGLIST3(RegARM32, s9, d4, q2)) \

98 X(Reg_s20, 20, "s20", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d10, q5)) \	120 X(Reg_s10, 10, "s10", 11, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

99 X(Reg_s21, 21, "s21", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d10, q5)) \	121 REGLIST3(RegARM32, s10, d5, q2)) \

100 X(Reg_s22, 22, "s22", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d11, q5)) \	122 X(Reg_s11, 11, "s11", 12, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

101 X(Reg_s23, 23, "s23", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d11, q5)) \	123 REGLIST3(RegARM32, s11, d5, q2)) \

102 X(Reg_s24, 24, "s24", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d12, q6)) \	124 X(Reg_s12, 12, "s12", 13, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

103 X(Reg_s25, 25, "s25", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d12, q6)) \	125 REGLIST3(RegARM32, s12, d6, q3)) \

104 X(Reg_s26, 26, "s26", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d13, q6)) \	126 X(Reg_s13, 13, "s13", 14, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

105 X(Reg_s27, 27, "s27", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d13, q6)) \	127 REGLIST3(RegARM32, s13, d6, q3)) \

106 X(Reg_s28, 28, "s28", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d14, q7)) \	128 X(Reg_s14, 14, "s14", 15, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

107 X(Reg_s29, 29, "s29", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d14, q7)) \	129 REGLIST3(RegARM32, s14, d7, q3)) \

108 X(Reg_s30, 30, "s30", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d15, q7)) \	130 X(Reg_s15, 15, "s15", 16, 1, 0, 0, 0, 0, 0, 1, 0, 0, \

109 X(Reg_s31, 31, "s31", 0,1,0,0, 0,0,1,0,0, REGLIST2(RegARM32, d15, q7))	131 REGLIST3(RegARM32, s15, d7, q3)) \

110 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,	132 X(Reg_s16, 16, "s16", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	133 REGLIST3(RegARM32, s16, d8, q4)) \

	134 X(Reg_s17, 17, "s17", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	135 REGLIST3(RegARM32, s17, d8, q4)) \

	136 X(Reg_s18, 18, "s18", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	137 REGLIST3(RegARM32, s18, d9, q4)) \

	138 X(Reg_s19, 19, "s19", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	139 REGLIST3(RegARM32, s19, d9, q4)) \

	140 X(Reg_s20, 20, "s20", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	141 REGLIST3(RegARM32, s20, d10, q5)) \

	142 X(Reg_s21, 21, "s21", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	143 REGLIST3(RegARM32, s21, d10, q5)) \

	144 X(Reg_s22, 22, "s22", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	145 REGLIST3(RegARM32, s22, d11, q5)) \

	146 X(Reg_s23, 23, "s23", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	147 REGLIST3(RegARM32, s23, d11, q5)) \

	148 X(Reg_s24, 24, "s24", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	149 REGLIST3(RegARM32, s24, d12, q6)) \

	150 X(Reg_s25, 25, "s25", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	151 REGLIST3(RegARM32, s25, d12, q6)) \

	152 X(Reg_s26, 26, "s26", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	153 REGLIST3(RegARM32, s26, d13, q6)) \

	154 X(Reg_s27, 27, "s27", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	155 REGLIST3(RegARM32, s27, d13, q6)) \

	156 X(Reg_s28, 28, "s28", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	157 REGLIST3(RegARM32, s28, d14, q7)) \

	158 X(Reg_s29, 29, "s29", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	159 REGLIST3(RegARM32, s29, d14, q7)) \

	160 X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	161 REGLIST3(RegARM32, s30, d15, q7)) \

	162 X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, \

	163 REGLIST3(RegARM32, s31, d14, q7))

	164 //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,

111 // isInt, isI64Pair, isFP32,isFP64, isVec128, alias_init)	165 // isInt, isI64Pair, isFP32,isFP64, isVec128, alias_init)

112	166

113 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch	167 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch

114 // (if supported by the D32 feature vs D16). D registers are defined in reverse	168 // (if supported by the D32 feature vs D16). D registers are defined in reverse

115 // order so that, during register allocation, Subzero will prefer higher D	169 // order so that, during register allocation, Subzero will prefer higher D

116 // registers. In processors supporting the D32 feature this will effectively	170 // registers. In processors supporting the D32 feature this will effectively

117 // cause double allocation to bias towards allocating "high" D registers, which	171 // cause double allocation to bias towards allocating "high" D registers, which

118 // do not alias any S registers.	172 // do not alias any S registers.

119 #define REGARM32_FP64_TABLE \	173 #define REGARM32_FP64_TABLE \

120 /* val, encode, name, scratch,preserved,stackptr,frameptr, \	174 /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \

121 isInt,isI64Pair,isFP32,isFP64,isVec128, alias_init */ \	175 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \

122 X(Reg_d31, 31, "d31", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q15)) \	176 X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

123 X(Reg_d30, 30, "d30", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q15)) \	177 REGLIST2(RegARM32, d31, q15)) \

124 X(Reg_d29, 29, "d29", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q14)) \	178 X(Reg_d30, 30, "d30", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

125 X(Reg_d28, 28, "d28", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q14)) \	179 REGLIST2(RegARM32, d30, q15)) \

126 X(Reg_d27, 27, "d27", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q13)) \	180 X(Reg_d29, 29, "d29", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

127 X(Reg_d26, 26, "d26", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q13)) \	181 REGLIST2(RegARM32, d29, q14)) \

128 X(Reg_d25, 25, "d25", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q12)) \	182 X(Reg_d28, 28, "d28", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

129 X(Reg_d24, 24, "d24", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q12)) \	183 REGLIST2(RegARM32, d28, q14)) \

130 X(Reg_d23, 23, "d23", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q11)) \	184 X(Reg_d27, 27, "d27", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

131 X(Reg_d22, 22, "d22", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q11)) \	185 REGLIST2(RegARM32, d27, q13)) \

132 X(Reg_d21, 21, "d21", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q10)) \	186 X(Reg_d26, 26, "d26", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

133 X(Reg_d20, 20, "d20", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q10)) \	187 REGLIST2(RegARM32, d26, q13)) \

134 X(Reg_d19, 19, "d19", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q9)) \	188 X(Reg_d25, 25, "d25", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

135 X(Reg_d18, 18, "d18", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q9)) \	189 REGLIST2(RegARM32, d25, q12)) \

136 X(Reg_d17, 17, "d17", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q8)) \	190 X(Reg_d24, 24, "d24", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

137 X(Reg_d16, 16, "d16", 1,0,0,0, 0,0,0,1,0, REGLIST1(RegARM32, q8)) \	191 REGLIST2(RegARM32, d24, q12)) \

138 X(Reg_d15, 15, "d15", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s30, s31, q7)) \	192 X(Reg_d23, 23, "d23", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

139 X(Reg_d14, 14, "d14", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s28, s29, q7)) \	193 REGLIST2(RegARM32, d23, q11)) \

140 X(Reg_d13, 13, "d13", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s26, s27, q6)) \	194 X(Reg_d22, 22, "d22", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

141 X(Reg_d12, 12, "d12", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s24, s25, q6)) \	195 REGLIST2(RegARM32, d22, q11)) \

142 X(Reg_d11, 11, "d11", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s22, s23, q5)) \	196 X(Reg_d21, 21, "d21", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

143 X(Reg_d10, 10, "d10", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s20, s21, q5)) \	197 REGLIST2(RegARM32, d21, q10)) \

144 X(Reg_d9, 9, "d9", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s18, s19, q4)) \	198 X(Reg_d20, 20, "d20", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

145 X(Reg_d8, 8, "d8", 0,1,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s16, s17, q4)) \	199 REGLIST2(RegARM32, d20, q10)) \

146 X(Reg_d7, 7, "d7", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s14, s15, q3)) \	200 X(Reg_d19, 19, "d19", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

147 X(Reg_d6, 6, "d6", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s12, s13, q3)) \	201 REGLIST2(RegARM32, d19, q9)) \

148 X(Reg_d5, 5, "d5", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s10, s11, q2)) \	202 X(Reg_d18, 18, "d18", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

149 X(Reg_d4, 4, "d4", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s8, s9, q2)) \	203 REGLIST2(RegARM32, d18, q9)) \

150 X(Reg_d3, 3, "d3", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s6, s7, q1)) \	204 X(Reg_d17, 17, "d17", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

151 X(Reg_d2, 2, "d2", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s4, s5, q1)) \	205 REGLIST2(RegARM32, d17, q8)) \

152 X(Reg_d1, 1, "d1", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s2, s3, q0)) \	206 X(Reg_d16, 16, "d16", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

153 X(Reg_d0, 0, "d0", 1,0,0,0, 0,0,0,1,0, REGLIST3(RegARM32, s0, s1, q0))	207 REGLIST2(RegARM32, d16, q8)) \

154 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,	208 X(Reg_d15, 15, "d15", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, \

	209 REGLIST4(RegARM32, d15, q7, s30, s31)) \

	210 X(Reg_d14, 14, "d14", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, \

	211 REGLIST4(RegARM32, d14, q7, s28, s28)) \

	212 X(Reg_d13, 13, "d13", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, \

	213 REGLIST4(RegARM32, d13, q6, s26, s27)) \

	214 X(Reg_d12, 12, "d12", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, \

	215 REGLIST4(RegARM32, d12, q6, s24, s25)) \

	216 X(Reg_d11, 11, "d11", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, \

	217 REGLIST4(RegARM32, d11, q5, s22, s24)) \

	218 X(Reg_d10, 10, "d10", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, \

	219 REGLIST4(RegARM32, d10, q5, s20, s21)) \

	220 X(Reg_d9, 9, "d9", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, \

	221 REGLIST4(RegARM32, d9, q4, s18, s19)) \

	222 X(Reg_d8, 8, "d8", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, \

	223 REGLIST4(RegARM32, d8, q4, s16, s17)) \

	224 X(Reg_d7, 7, "d7", 8, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

	225 REGLIST4(RegARM32, d7, q3, s14, s15)) \

	226 X(Reg_d6, 6, "d6", 7, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

	227 REGLIST4(RegARM32, d6, q3, s12, s13)) \

	228 X(Reg_d5, 5, "d5", 6, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

	229 REGLIST4(RegARM32, d5, q2, s10, s11)) \

	230 X(Reg_d4, 4, "d4", 5, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

	231 REGLIST4(RegARM32, d4, q2, s8, s9)) \

	232 X(Reg_d3, 3, "d3", 4, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

	233 REGLIST4(RegARM32, d3, q1, s6, s7)) \

	234 X(Reg_d2, 2, "d2", 3, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

	235 REGLIST4(RegARM32, d2, q1, s4, s5)) \

	236 X(Reg_d1, 1, "d1", 2, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

	237 REGLIST4(RegARM32, d1, q0, s2, s3)) \

	238 X(Reg_d0, 0, "d0", 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, \

	239 REGLIST4(RegARM32, d0, q0, s0, s1))

	240 //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,

155 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)	241 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)

156	242

157 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch	243 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch

158 // (if supported by the D32 feature). Q registers are defined in reverse order	244 // (if supported by the D32 feature). Q registers are defined in reverse order

159 // for the same reason as D registers.	245 // for the same reason as D registers.

160 #define REGARM32_VEC128_TABLE \	246 #define REGARM32_VEC128_TABLE \

161 /* val, encode, name, scratch, preserved, stackptr, frameptr, \	247 /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \

162 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \	248 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \

163 X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	249 X(Reg_q15, 15, "q15", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

164 REGLIST2(RegARM32, d30, d31)) \	250 REGLIST3(RegARM32, q15, d30, d31)) \

165 X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	251 X(Reg_q14, 14, "q14", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

166 REGLIST2(RegARM32, d28, d29)) \	252 REGLIST3(RegARM32, q14, d28, d29)) \

167 X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	253 X(Reg_q13, 13, "q13", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

168 REGLIST2(RegARM32, d26, d27)) \	254 REGLIST3(RegARM32, q13, d26, d27)) \

169 X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	255 X(Reg_q12, 12, "q12", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

170 REGLIST2(RegARM32, d24, d25)) \	256 REGLIST3(RegARM32, q12, d24, d25)) \

171 X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	257 X(Reg_q11, 11, "q11", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

172 REGLIST2(RegARM32, d22, d23)) \	258 REGLIST3(RegARM32, q11, d22, d23)) \

173 X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	259 X(Reg_q10, 10, "q10", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

174 REGLIST2(RegARM32, d20, d21)) \	260 REGLIST3(RegARM32, q10, d20, d21)) \

175 X(Reg_q9, 9, "q9", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	261 X(Reg_q9, 9, "q9", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

176 REGLIST2(RegARM32, d18, d19)) \	262 REGLIST3(RegARM32, q9, d18, d19)) \

177 X(Reg_q8, 8, "q8", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	263 X(Reg_q8, 8, "q8", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

178 REGLIST2(RegARM32, d16, d17)) \	264 REGLIST3(RegARM32, q8, d16, d17)) \

179 X(Reg_q7, 7, "q7", 0, 1, 0, 0, 0, 0, 0, 0, 1, \	265 X(Reg_q7, 7, "q7", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, \

180 REGLIST6(RegARM32, s28, s29, s30, s31, d14, d15)) \	266 REGLIST7(RegARM32, q7, d14, d15, s28, s29, s30, s31)) \

181 X(Reg_q6, 6, "q6", 0, 1, 0, 0, 0, 0, 0, 0, 1, \	267 X(Reg_q6, 6, "q6", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, \

182 REGLIST6(RegARM32, s24, s25, s26, s27, d12, d13)) \	268 REGLIST7(RegARM32, q6, d12, d13, s24, s25, s26, s27)) \

183 X(Reg_q5, 5, "q5", 0, 1, 0, 0, 0, 0, 0, 0, 1, \	269 X(Reg_q5, 5, "q5", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, \

184 REGLIST6(RegARM32, s20, s21, s22, s23, d10, d11)) \	270 REGLIST7(RegARM32, q5, d10, d11, s20, s21, s22, s23)) \

185 X(Reg_q4, 4, "q4", 0, 1, 0, 0, 0, 0, 0, 0, 1, \	271 X(Reg_q4, 4, "q4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, \

186 REGLIST6(RegARM32, s16, s17, s18, s19, d8, d9)) \	272 REGLIST7(RegARM32, q4, d8, d9, s16, s17, s18, s19)) \

187 X(Reg_q3, 3, "q3", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	273 X(Reg_q3, 3, "q3", 4, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

188 REGLIST6(RegARM32, s12, s13, s14, s15, d6, d7)) \	274 REGLIST7(RegARM32, q3, d6, d7, s12, s13, s14, s15)) \

189 X(Reg_q2, 2, "q2", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	275 X(Reg_q2, 2, "q2", 3, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

190 REGLIST6(RegARM32, s8, s9, s10, s11, d4, d5)) \	276 REGLIST7(RegARM32, q2, d4, d5, s8, s9, s10, s11)) \

191 X(Reg_q1, 1, "q1", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	277 X(Reg_q1, 1, "q1", 2, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

192 REGLIST6(RegARM32, s4, s5, s6, s7, d2, d3)) \	278 REGLIST7(RegARM32, q1, d2, d3, s4, s5, s6, s7)) \

193 X(Reg_q0, 0, "q0", 1, 0, 0, 0, 0, 0, 0, 0, 1, \	279 X(Reg_q0, 0, "q0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, \

194 REGLIST6(RegARM32, s0, s1, s2, s3, d0, d1))	280 REGLIST7(RegARM32, q0, d0, d1, s0, s1, s2, s3))

195 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,	281 //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,

196 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)	282 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)

197	283

198 // We also provide a combined table, so that there is a namespace where all of	284 // We also provide a combined table, so that there is a namespace where all of

199 // the registers are considered and have distinct numberings. This is in	285 // the registers are considered and have distinct numberings. This is in

200 // contrast to the above, where the "encode" is based on how the register	286 // contrast to the above, where the "encode" is based on how the register

201 // numbers will be encoded in binaries and values can overlap.	287 // numbers will be encoded in binaries and values can overlap.

202 #define REGARM32_TABLE \	288 #define REGARM32_TABLE \

203 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \	289 /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \

204 isFP32, isFP64, isVec128, alias_init */ \	290 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \

205 REGARM32_GPR_TABLE \	291 REGARM32_GPR_TABLE \

206 REGARM32_I64PAIR_TABLE \	292 REGARM32_I64PAIR_TABLE \

207 REGARM32_FP32_TABLE \	293 REGARM32_FP32_TABLE \

208 REGARM32_FP64_TABLE \	294 REGARM32_FP64_TABLE \

209 REGARM32_VEC128_TABLE	295 REGARM32_VEC128_TABLE

210 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,	296 //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,

211 // isInt, isFP32, isFP64, isVec128, alias_init)	297 // isInt, isFP32, isFP64, isVec128, alias_init)

212	298

213 #define REGARM32_TABLE_BOUNDS \	299 #define REGARM32_TABLE_BOUNDS \

214 /* val, init */ \	300 /* val, init */ \

215 X(Reg_GPR_First, = Reg_r0) \	301 X(Reg_GPR_First, = Reg_r0) \

216 X(Reg_GPR_Last, = Reg_pc) \	302 X(Reg_GPR_Last, = Reg_pc) \

217 X(Reg_I64PAIR_First, = Reg_r0r1) \	303 X(Reg_I64PAIR_First, = Reg_r0r1) \

218 X(Reg_I64PAIR_Last, = Reg_r10fp) \	304 X(Reg_I64PAIR_Last, = Reg_r10fp) \

219 X(Reg_SREG_First, = Reg_s0) \	305 X(Reg_SREG_First, = Reg_s0) \

220 X(Reg_SREG_Last, = Reg_s31) \	306 X(Reg_SREG_Last, = Reg_s31) \

(...skipping 53 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
274 X(LS, 9, HI, "ls") /* unsigned lower or same */ \	360 X(LS, 9, HI, "ls") /* unsigned lower or same */ \

275 X(GE, 10, LT, "ge") /* signed greater than or equal */ \	361 X(GE, 10, LT, "ge") /* signed greater than or equal */ \

276 X(LT, 11, GE, "lt") /* signed less than */ \	362 X(LT, 11, GE, "lt") /* signed less than */ \

277 X(GT, 12, LE, "gt") /* signed greater than */ \	363 X(GT, 12, LE, "gt") /* signed greater than */ \

278 X(LE, 13, GT, "le") /* signed less than or equal */ \	364 X(LE, 13, GT, "le") /* signed less than or equal */ \

279 X(AL, 14, kNone, "") /* always (unconditional) */ \	365 X(AL, 14, kNone, "") /* always (unconditional) */ \

280 X(kNone, 15, kNone, "??") /* special condition / none */	366 X(kNone, 15, kNone, "??") /* special condition / none */

281 //#define X(tag, encode, opp, emit)	367 //#define X(tag, encode, opp, emit)

282	368

283 #endif // SUBZERO_SRC_ICEINSTARM32_DEF	369 #endif // SUBZERO_SRC_ICEINSTARM32_DEF

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