Fixes for integer division on ARM hardware so that assembler tests pass.

runtime/vm/assembler_arm_test.cc

Index: runtime/vm/assembler_arm_test.cc
===================================================================
--- runtime/vm/assembler_arm_test.cc	(revision 22334)
+++ runtime/vm/assembler_arm_test.cc	(working copy)
@@ -1422,7 +1422,6 @@
   EXPECT_EQ(0, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
   CPUFeatures::set_integer_division_supported(b);
 }
-#endif  // defined(USING_SIMULATOR)
 
 
 ASSEMBLER_TEST_GENERATE(MrcReal, assembler) {
@@ -1444,13 +1443,18 @@
     EXPECT_EQ(0, r);
   }
 }
+#endif  // defined(USING_SIMULATOR)
 
 
 ASSEMBLER_TEST_GENERATE(Udiv, assembler) {
-  __ mov(R0, ShifterOperand(27));
-  __ mov(R1, ShifterOperand(9));
-  __ udiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ mov(R0, ShifterOperand(27));
+    __ mov(R1, ShifterOperand(9));
+    __ udiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ mov(R0, ShifterOperand(3));
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
@@ -1463,10 +1467,14 @@
 
 
 ASSEMBLER_TEST_GENERATE(Sdiv, assembler) {
-  __ mov(R0, ShifterOperand(27));
-  __ LoadImmediate(R1, -9);
-  __ sdiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ mov(R0, ShifterOperand(27));
+    __ LoadImmediate(R1, -9);
+    __ sdiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ LoadImmediate(R0, -3);
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
@@ -1479,10 +1487,14 @@
 
 
 ASSEMBLER_TEST_GENERATE(Udiv_zero, assembler) {
-  __ mov(R0, ShifterOperand(27));
-  __ mov(R1, ShifterOperand(0));
-  __ udiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ mov(R0, ShifterOperand(27));
+    __ mov(R1, ShifterOperand(0));
+    __ udiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ LoadImmediate(R0, 0);
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
@@ -1495,10 +1507,14 @@
 
 
 ASSEMBLER_TEST_GENERATE(Sdiv_zero, assembler) {
-  __ mov(R0, ShifterOperand(27));
-  __ mov(R1, ShifterOperand(0));
-  __ udiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ mov(R0, ShifterOperand(27));
+    __ mov(R1, ShifterOperand(0));
+    __ udiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ LoadImmediate(R0, 0);
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
@@ -1511,10 +1527,14 @@
 
 
 ASSEMBLER_TEST_GENERATE(Udiv_corner, assembler) {
-  __ LoadImmediate(R0, 0x80000000);
-  __ LoadImmediate(R1, 0xffffffff);
-  __ udiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ LoadImmediate(R0, 0x80000000);
+    __ LoadImmediate(R1, 0xffffffff);
+    __ udiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ LoadImmediate(R0, 0);
+  }
   __ mov(PC, ShifterOperand(LR));
 }
 
@@ -1527,10 +1547,14 @@
 
 
 ASSEMBLER_TEST_GENERATE(Sdiv_corner, assembler) {
-  __ LoadImmediate(R0, 0x80000000);
-  __ LoadImmediate(R1, 0xffffffff);
-  __ sdiv(R2, R0, R1);
-  __ Mov(R0, R2);
+  if (CPUFeatures::integer_division_supported()) {
+    __ LoadImmediate(R0, 0x80000000);
+    __ LoadImmediate(R1, 0xffffffff);
+    __ sdiv(R2, R0, R1);
+    __ Mov(R0, R2);
+  } else {
+    __ LoadImmediate(R0, 0x80000000);
+  }
   __ mov(PC, ShifterOperand(LR));
 }