Add the PUSH instruction to ARM integrated assembler.

src/IceAssemblerARM32.h

Index: src/IceAssemblerARM32.h
diff --git a/src/IceAssemblerARM32.h b/src/IceAssemblerARM32.h
index 95b23a2b2d4fccb8233b667188f1f97861764fea..992b511d88468de9fdbf530b495d45f1274d8606 100644
--- a/src/IceAssemblerARM32.h
+++ b/src/IceAssemblerARM32.h
@@ -189,6 +189,11 @@ public:
   void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
+  void push(const Operand *OpRt, CondARM32::Cond Cond);
+
+  // Note: Registers is a bitset, where bit n corresponds to register Rn.
+  void pushList(const IValueT Registers, CondARM32::Cond Cond);
+
   void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
@@ -221,6 +226,19 @@ private:
   // InstARM32::emitUsingTextFixup().
   size_t EmitTextSize = 0;
 
+  // Load/store multiple addressing mode.
+  enum BlockAddressMode {
+    // bit encoding P U W
+    DA = (0 | 0 | 0) << 21,   // decrement after
+    IA = (0 | 4 | 0) << 21,   // increment after
+    DB = (8 | 0 | 0) << 21,   // decrement before
+    IB = (8 | 4 | 0) << 21,   // increment before
+    DA_W = (0 | 0 | 1) << 21, // decrement after with writeback to base
+    IA_W = (0 | 4 | 1) << 21, // increment after with writeback to base
+    DB_W = (8 | 0 | 1) << 21, // decrement before with writeback to base
+    IB_W = (8 | 4 | 1) << 21  // increment before with writeback to base
+  };
+
   Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
 
   void bindCfgNodeLabel(const CfgNode *Node) override;
@@ -259,6 +277,12 @@ private:
   void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad,
                  bool IsByte, uint32_t Rt, uint32_t Address);
 
+  // Pattern cccc100aaaalnnnnrrrrrrrrrrrrrrrr where cccc=Cond,
+  // aaaa<<21=AddressMode, l=IsLoad, nnnn=BaseReg, and
+  // rrrrrrrrrrrrrrrr is bitset of Registers.
+  void emitMultiMemOp(CondARM32::Cond Cond, BlockAddressMode AddressMode,
+                      bool IsLoad, IValueT BaseReg, IValueT Registers);
+
   // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond,
   // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
   void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,