Add the PUSH instruction to ARM integrated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 171 matching lines @@
 
   void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm,
            const Operand *OpRa, CondARM32::Cond Cond);
 
   void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
+  void push(const Operand *OpRt, CondARM32::Cond Cond);
+
+  // Note: Registers is a bitset, where bit n corresponds to register Rn.
+  void pushList(const IValueT Registers, CondARM32::Cond Cond);
+
   void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
   void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
             CondARM32::Cond Cond);
 
   void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond);
 
   void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
@@ skipping 12 matching lines @@
 private:
   // A vector of pool-allocated x86 labels for CFG nodes.
   using LabelVector = std::vector<Label *>;
   LabelVector CfgNodeLabels;
   // A vector of pool-allocated x86 labels for Local labels.
   LabelVector LocalLabels;
   // Number of bytes emitted by InstARM32::emit() methods, when run inside
   // InstARM32::emitUsingTextFixup().
   size_t EmitTextSize = 0;
 
+  // Load/store multiple addressing mode.
+  enum BlockAddressMode {
+    // bit encoding P U W
+    DA = (0 | 0 | 0) << 21,   // decrement after
+    IA = (0 | 4 | 0) << 21,   // increment after
+    DB = (8 | 0 | 0) << 21,   // decrement before
+    IB = (8 | 4 | 0) << 21,   // increment before
+    DA_W = (0 | 0 | 1) << 21, // decrement after with writeback to base
+    IA_W = (0 | 4 | 1) << 21, // increment after with writeback to base
+    DB_W = (8 | 0 | 1) << 21, // decrement before with writeback to base
+    IB_W = (8 | 4 | 1) << 21  // increment before with writeback to base
+  };
+
   Label *getOrCreateLabel(SizeT Number, LabelVector &Labels);
 
   void bindCfgNodeLabel(const CfgNode *Node) override;
 
   void emitInst(IValueT Value) { Buffer.emit<IValueT>(Value); }
 
   // Pattern cccctttoooosnnnnddddiiiiiiiiiiii where cccc=Cond, ttt=Type,
   // oooo=Opcode, nnnn=Rn, dddd=Rd, iiiiiiiiiiii=imm12 (See ARM section A5.2.3).
   void emitType01(CondARM32::Cond Cond, IValueT Type, IValueT Opcode,
                   bool SetCc, IValueT Rn, IValueT Rd, IValueT imm12);
@@ skipping 18 matching lines @@
 
   void emitType05(CondARM32::Cond COnd, int32_t Offset, bool Link);
 
   // Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType,
   // l=isLoad, b=isByte, and aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that
   // Address is assumed to be defined by decodeAddress() in
   // IceAssemblerARM32.cpp.
   void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad,
                  bool IsByte, uint32_t Rt, uint32_t Address);
 
+  // Pattern cccc100aaaalnnnnrrrrrrrrrrrrrrrr where cccc=Cond,
+  // aaaa<<21=AddressMode, l=IsLoad, nnnn=BaseReg, and
+  // rrrrrrrrrrrrrrrr is bitset of Registers.
+  void emitMultiMemOp(CondARM32::Cond Cond, BlockAddressMode AddressMode,
+                      bool IsLoad, IValueT BaseReg, IValueT Registers);
+
   // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond,
   // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
   void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm);
 
   // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, ssss=Rs, f=SetCc, and xxxxxxx=Opcode.
   void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm, IValueT Rs, bool SetCc);
 
   // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn,
   // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from
   // OpSrc1, and xxxx=Opcode.
   void emitCompareOp(IValueT Opcode, const Operand *OpRn, const Operand *OpSrc1,
                      CondARM32::Cond Cond);
 
   void emitBranch(Label *L, CondARM32::Cond, bool Link);
 
   // Encodes the given Offset into the branch instruction Inst.
   IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
 
   // Returns the offset encoded in the branch instruction Inst.
   static IOffsetT decodeBranchOffset(IValueT Inst);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H