MIPS: r6 compact branch optimization.

src/mips/assembler-mips.h

Index: src/mips/assembler-mips.h
diff --git a/src/mips/assembler-mips.h b/src/mips/assembler-mips.h
index 7f5b96714d864c62e33413247f6c1654b61934ff..04b91466dbfcf521914cdada2e497dde1c838765 100644
--- a/src/mips/assembler-mips.h
+++ b/src/mips/assembler-mips.h
@@ -415,20 +415,25 @@ class Assembler : public AssemblerBase {
   // Returns the branch offset to the given label from the current code
   // position. Links the label to the current position if it is still unbound.
   // Manages the jump elimination optimization if the second parameter is true.
-  int32_t branch_offset(Label* L, bool jump_elimination_allowed);
-  int32_t branch_offset_compact(Label* L, bool jump_elimination_allowed);
-  int32_t branch_offset21(Label* L, bool jump_elimination_allowed);
-  int32_t branch_offset21_compact(Label* L, bool jump_elimination_allowed);
+  int32_t branch_offset_helper(Label* L, bool jump_elimination_allowed,
+                               int bits);
+  int32_t branch_offset(Label* L, bool jump_elimination_allowed) {
+    return branch_offset_helper(L, jump_elimination_allowed, 16);

[ivica.bogosavljevic, 2015/10/15 11:49:08]

It would be nice to have these three functions inlined (though I am not sure if
we profit with this): branch_offset, branch_offset21 and branch_offset26.
Also, the numbers 16, 21 and 26 should be replaced with named constants

[balazs.kilvady, 2015/10/30 21:11:14]

Done.

+  }
+  int32_t branch_offset21(Label* L, bool jump_elimination_allowed) {
+    return branch_offset_helper(L, jump_elimination_allowed, 21);
+  }
+  int32_t branch_offset26(Label* L, bool jump_elimination_allowed) {
+    return branch_offset_helper(L, jump_elimination_allowed, 26);
+  }
   int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) {
-    int32_t o = branch_offset(L, jump_elimination_allowed);
-    DCHECK((o & 3) == 0);   // Assert the offset is aligned.
-    return o >> 2;
+    return branch_offset(L, jump_elimination_allowed) >> 2;
+  }
+  int32_t shifted_branch_offset21(Label* L, bool jump_elimination_allowed) {
+    return branch_offset21(L, jump_elimination_allowed) >> 2;
   }
-  int32_t shifted_branch_offset_compact(Label* L,
-      bool jump_elimination_allowed) {
-    int32_t o = branch_offset_compact(L, jump_elimination_allowed);
-    DCHECK((o & 3) == 0);   // Assert the offset is aligned.
-    return o >> 2;
+  int32_t shifted_branch_offset26(Label* L, bool jump_elimination_allowed) {
+    return branch_offset26(L, jump_elimination_allowed) >> 2;
   }
   uint32_t jump_address(Label* L);
 
@@ -571,35 +576,35 @@ class Assembler : public AssemblerBase {
   // --------Branch-and-jump-instructions----------
   // We don't use likely variant of instructions.
   void b(int16_t offset);
-  void b(Label* L) { b(branch_offset(L, false)>>2); }
+  void b(Label* L) { b(shifted_branch_offset(L, false)); }

[ivica.bogosavljevic, 2015/10/15 11:49:08]

Mark inline small functions

[balazs.kilvady, 2015/10/30 21:11:14]

Done.

   void bal(int16_t offset);
-  void bal(Label* L) { bal(branch_offset(L, false)>>2); }
+  void bal(Label* L) { bal(shifted_branch_offset(L, false)); }
   void bc(int32_t offset);
-  void bc(Label* L) { bc(branch_offset(L, false) >> 2); }
+  void bc(Label* L) { bc(shifted_branch_offset26(L, false)); }
   void balc(int32_t offset);
-  void balc(Label* L) { balc(branch_offset(L, false) >> 2); }
+  void balc(Label* L) { balc(shifted_branch_offset26(L, false)); }
 
   void beq(Register rs, Register rt, int16_t offset);
   void beq(Register rs, Register rt, Label* L) {
-    beq(rs, rt, branch_offset(L, false) >> 2);
+    beq(rs, rt, shifted_branch_offset(L, false));
   }
   void bgez(Register rs, int16_t offset);
   void bgezc(Register rt, int16_t offset);
   void bgezc(Register rt, Label* L) {
-    bgezc(rt, branch_offset_compact(L, false)>>2);
+    bgezc(rt, shifted_branch_offset(L, false));
   }
   void bgeuc(Register rs, Register rt, int16_t offset);
   void bgeuc(Register rs, Register rt, Label* L) {
-    bgeuc(rs, rt, branch_offset_compact(L, false)>>2);
+    bgeuc(rs, rt, shifted_branch_offset(L, false));
   }
   void bgec(Register rs, Register rt, int16_t offset);
   void bgec(Register rs, Register rt, Label* L) {
-    bgec(rs, rt, branch_offset_compact(L, false)>>2);
+    bgec(rs, rt, shifted_branch_offset(L, false));
   }
   void bgezal(Register rs, int16_t offset);
   void bgezalc(Register rt, int16_t offset);
   void bgezalc(Register rt, Label* L) {
-    bgezalc(rt, branch_offset_compact(L, false)>>2);
+    bgezalc(rt, shifted_branch_offset(L, false));
   }
   void bgezall(Register rs, int16_t offset);
   void bgezall(Register rs, Label* L) {
@@ -608,74 +613,74 @@ class Assembler : public AssemblerBase {
   void bgtz(Register rs, int16_t offset);
   void bgtzc(Register rt, int16_t offset);
   void bgtzc(Register rt, Label* L) {
-    bgtzc(rt, branch_offset_compact(L, false)>>2);
+    bgtzc(rt, shifted_branch_offset(L, false));
   }
   void blez(Register rs, int16_t offset);
   void blezc(Register rt, int16_t offset);
   void blezc(Register rt, Label* L) {
-    blezc(rt, branch_offset_compact(L, false)>>2);
+    blezc(rt, shifted_branch_offset(L, false));
   }
   void bltz(Register rs, int16_t offset);
   void bltzc(Register rt, int16_t offset);
   void bltzc(Register rt, Label* L) {
-    bltzc(rt, branch_offset_compact(L, false)>>2);
+    bltzc(rt, shifted_branch_offset(L, false));
   }
   void bltuc(Register rs, Register rt, int16_t offset);
   void bltuc(Register rs, Register rt, Label* L) {
-    bltuc(rs, rt, branch_offset_compact(L, false)>>2);
+    bltuc(rs, rt, shifted_branch_offset(L, false));
   }
   void bltc(Register rs, Register rt, int16_t offset);
   void bltc(Register rs, Register rt, Label* L) {
-    bltc(rs, rt, branch_offset_compact(L, false)>>2);
+    bltc(rs, rt, shifted_branch_offset(L, false));
   }
   void bltzal(Register rs, int16_t offset);
   void blezalc(Register rt, int16_t offset);
   void blezalc(Register rt, Label* L) {
-    blezalc(rt, branch_offset_compact(L, false)>>2);
+    blezalc(rt, shifted_branch_offset(L, false));
   }
   void bltzalc(Register rt, int16_t offset);
   void bltzalc(Register rt, Label* L) {
-    bltzalc(rt, branch_offset_compact(L, false)>>2);
+    bltzalc(rt, shifted_branch_offset(L, false));
   }
   void bgtzalc(Register rt, int16_t offset);
   void bgtzalc(Register rt, Label* L) {
-    bgtzalc(rt, branch_offset_compact(L, false)>>2);
+    bgtzalc(rt, shifted_branch_offset(L, false));
   }
   void beqzalc(Register rt, int16_t offset);
   void beqzalc(Register rt, Label* L) {
-    beqzalc(rt, branch_offset_compact(L, false)>>2);
+    beqzalc(rt, shifted_branch_offset(L, false));
   }
   void beqc(Register rs, Register rt, int16_t offset);
   void beqc(Register rs, Register rt, Label* L) {
-    beqc(rs, rt, branch_offset_compact(L, false)>>2);
+    beqc(rs, rt, shifted_branch_offset(L, false));
   }
   void beqzc(Register rs, int32_t offset);
   void beqzc(Register rs, Label* L) {
-    beqzc(rs, branch_offset21_compact(L, false)>>2);
+    beqzc(rs, shifted_branch_offset21(L, false));
   }
   void bnezalc(Register rt, int16_t offset);
   void bnezalc(Register rt, Label* L) {
-    bnezalc(rt, branch_offset_compact(L, false)>>2);
+    bnezalc(rt, shifted_branch_offset(L, false));
   }
   void bnec(Register rs, Register rt, int16_t offset);
   void bnec(Register rs, Register rt, Label* L) {
-    bnec(rs, rt, branch_offset_compact(L, false)>>2);
+    bnec(rs, rt, shifted_branch_offset(L, false));
   }
   void bnezc(Register rt, int32_t offset);
   void bnezc(Register rt, Label* L) {
-    bnezc(rt, branch_offset21_compact(L, false)>>2);
+    bnezc(rt, shifted_branch_offset21(L, false));
   }
   void bne(Register rs, Register rt, int16_t offset);
   void bne(Register rs, Register rt, Label* L) {
-    bne(rs, rt, branch_offset(L, false)>>2);
+    bne(rs, rt, shifted_branch_offset(L, false));
   }
   void bovc(Register rs, Register rt, int16_t offset);
   void bovc(Register rs, Register rt, Label* L) {
-    bovc(rs, rt, branch_offset_compact(L, false)>>2);
+    bovc(rs, rt, shifted_branch_offset(L, false));
   }
   void bnvc(Register rs, Register rt, int16_t offset);
   void bnvc(Register rs, Register rt, Label* L) {
-    bnvc(rs, rt, branch_offset_compact(L, false)>>2);
+    bnvc(rs, rt, shifted_branch_offset(L, false));
   }
 
   // Never use the int16_t b(l)cond version with a branch offset
@@ -921,11 +926,11 @@ class Assembler : public AssemblerBase {
 
   void bc1eqz(int16_t offset, FPURegister ft);
   void bc1eqz(Label* L, FPURegister ft) {
-    bc1eqz(branch_offset(L, false)>>2, ft);
+    bc1eqz(shifted_branch_offset(L, false), ft);
   }
   void bc1nez(int16_t offset, FPURegister ft);
   void bc1nez(Label* L, FPURegister ft) {
-    bc1nez(branch_offset(L, false)>>2, ft);
+    bc1nez(shifted_branch_offset(L, false), ft);
   }
 
   // Conditions and branches for non MIPSr6.
@@ -935,9 +940,13 @@ class Assembler : public AssemblerBase {
   void c_d(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0);
 
   void bc1f(int16_t offset, uint16_t cc = 0);
-  void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); }
+  void bc1f(Label* L, uint16_t cc = 0) {
+    bc1f(shifted_branch_offset(L, false), cc);
+  }
   void bc1t(int16_t offset, uint16_t cc = 0);
-  void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); }
+  void bc1t(Label* L, uint16_t cc = 0) {
+    bc1t(shifted_branch_offset(L, false), cc);
+  }
   void fcmp(FPURegister src1, const double src2, FPUCondition cond);
 
   // Check the code size generated from label to here.
@@ -1056,8 +1065,14 @@ class Assembler : public AssemblerBase {
 
   // Check if an instruction is a branch of some kind.
   static bool IsBranch(Instr instr);
+  static bool IsBc(Instr instr);
+  static bool IsBzc(Instr instr);
   static bool IsBeq(Instr instr);
   static bool IsBne(Instr instr);
+  static bool IsBeqzc(Instr instr);
+  static bool IsBnezc(Instr instr);
+  static bool IsBeqc(Instr instr);
+  static bool IsBnec(Instr instr);
 
   static bool IsJump(Instr instr);
   static bool IsJ(Instr instr);
@@ -1179,6 +1194,8 @@ class Assembler : public AssemblerBase {
     return block_buffer_growth_;
   }
 
+  bool IsPrevInstrCompactBranch() { return prev_instr_compact_branch_; }
+
  private:
   inline static void set_target_internal_reference_encoded_at(Address pc,
                                                               Address target);
@@ -1365,12 +1382,17 @@ class Assembler : public AssemblerBase {
   bool trampoline_emitted_;
   static const int kTrampolineSlotsSize = 4 * kInstrSize;
   static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
+  static const int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1;
   static const int kInvalidSlotPos = -1;
 
   // Internal reference positions, required for unbounded internal reference
   // labels.
   std::set<int> internal_reference_positions_;
 
+  void EmittedCompactBranchInstruction() { prev_instr_compact_branch_ = true; }

[ivica.bogosavljevic, 2015/10/15 11:49:08]

The names of the functions EmittedCompactBranchInstruction and should be paired
for clarity ClearCompactBranchState, example:
MarkCompactBranchInstructionEmitted
ClearCompactBranchInstructionEmitted

[balazs.kilvady, 2015/10/30 21:11:14]

I don't agree, please discuss it with Paul.

+  void ClearCompactBranchState() { prev_instr_compact_branch_ = false; }
+  bool prev_instr_compact_branch_ = false;
+
   Trampoline trampoline_;
   bool internal_trampoline_exception_;