MIPS: r6 compact branch optimization.

src/mips/assembler-mips.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 397 matching lines @@
   // Note: The same Label can be used for forward and backward branches
   // but it may be bound only once.
   void bind(Label* L);  // Binds an unbound label L to current code position.
   // Determines if Label is bound and near enough so that branch instruction
   // can be used to reach it, instead of jump instruction.
   bool is_near(Label* L);
 
   // Returns the branch offset to the given label from the current code
   // position. Links the label to the current position if it is still unbound.
   // Manages the jump elimination optimization if the second parameter is true.
-  int32_t branch_offset(Label* L, bool jump_elimination_allowed);
-  int32_t branch_offset_compact(Label* L, bool jump_elimination_allowed);
-  int32_t branch_offset21(Label* L, bool jump_elimination_allowed);
-  int32_t branch_offset21_compact(Label* L, bool jump_elimination_allowed);
+  int32_t branch_offset_helper(Label* L, bool jump_elimination_allowed,
+                               int bits);
+  int32_t branch_offset(Label* L, bool jump_elimination_allowed) {
+    return branch_offset_helper(L, jump_elimination_allowed, 16);

[ivica.bogosavljevic, 2015/10/15 11:49:08]

It would be nice to have these three functions inlined (though I am not sure if
we profit with this): branch_offset, branch_offset21 and branch_offset26.
Also, the numbers 16, 21 and 26 should be replaced with named constants

[balazs.kilvady, 2015/10/30 21:11:14]

Done.

+  }
+  int32_t branch_offset21(Label* L, bool jump_elimination_allowed) {
+    return branch_offset_helper(L, jump_elimination_allowed, 21);
+  }
+  int32_t branch_offset26(Label* L, bool jump_elimination_allowed) {
+    return branch_offset_helper(L, jump_elimination_allowed, 26);
+  }
   int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) {
-    int32_t o = branch_offset(L, jump_elimination_allowed);
-    DCHECK((o & 3) == 0);   // Assert the offset is aligned.
-    return o >> 2;
+    return branch_offset(L, jump_elimination_allowed) >> 2;
   }
-  int32_t shifted_branch_offset_compact(Label* L,
-      bool jump_elimination_allowed) {
-    int32_t o = branch_offset_compact(L, jump_elimination_allowed);
-    DCHECK((o & 3) == 0);   // Assert the offset is aligned.
-    return o >> 2;
+  int32_t shifted_branch_offset21(Label* L, bool jump_elimination_allowed) {
+    return branch_offset21(L, jump_elimination_allowed) >> 2;
+  }
+  int32_t shifted_branch_offset26(Label* L, bool jump_elimination_allowed) {
+    return branch_offset26(L, jump_elimination_allowed) >> 2;
   }
   uint32_t jump_address(Label* L);
 
   // Puts a labels target address at the given position.
   // The high 8 bits are set to zero.
   void label_at_put(Label* L, int at_offset);
 
   // Read/Modify the code target address in the branch/call instruction at pc.
   static Address target_address_at(Address pc);
   static void set_target_address_at(Address pc,
@@ skipping 122 matching lines @@
   void nop(unsigned int type = 0) {
     DCHECK(type < 32);
     Register nop_rt_reg = (type == 0) ? zero_reg : at;
     sll(zero_reg, nop_rt_reg, type, true);
   }
 
 
   // --------Branch-and-jump-instructions----------
   // We don't use likely variant of instructions.
   void b(int16_t offset);
-  void b(Label* L) { b(branch_offset(L, false)>>2); }
+  void b(Label* L) { b(shifted_branch_offset(L, false)); }

[ivica.bogosavljevic, 2015/10/15 11:49:08]

Mark inline small functions

[balazs.kilvady, 2015/10/30 21:11:14]

Done.

   void bal(int16_t offset);
-  void bal(Label* L) { bal(branch_offset(L, false)>>2); }
+  void bal(Label* L) { bal(shifted_branch_offset(L, false)); }
   void bc(int32_t offset);
-  void bc(Label* L) { bc(branch_offset(L, false) >> 2); }
+  void bc(Label* L) { bc(shifted_branch_offset26(L, false)); }
   void balc(int32_t offset);
-  void balc(Label* L) { balc(branch_offset(L, false) >> 2); }
+  void balc(Label* L) { balc(shifted_branch_offset26(L, false)); }
 
   void beq(Register rs, Register rt, int16_t offset);
   void beq(Register rs, Register rt, Label* L) {
-    beq(rs, rt, branch_offset(L, false) >> 2);
+    beq(rs, rt, shifted_branch_offset(L, false));
   }
   void bgez(Register rs, int16_t offset);
   void bgezc(Register rt, int16_t offset);
   void bgezc(Register rt, Label* L) {
-    bgezc(rt, branch_offset_compact(L, false)>>2);
+    bgezc(rt, shifted_branch_offset(L, false));
   }
   void bgeuc(Register rs, Register rt, int16_t offset);
   void bgeuc(Register rs, Register rt, Label* L) {
-    bgeuc(rs, rt, branch_offset_compact(L, false)>>2);
+    bgeuc(rs, rt, shifted_branch_offset(L, false));
   }
   void bgec(Register rs, Register rt, int16_t offset);
   void bgec(Register rs, Register rt, Label* L) {
-    bgec(rs, rt, branch_offset_compact(L, false)>>2);
+    bgec(rs, rt, shifted_branch_offset(L, false));
   }
   void bgezal(Register rs, int16_t offset);
   void bgezalc(Register rt, int16_t offset);
   void bgezalc(Register rt, Label* L) {
-    bgezalc(rt, branch_offset_compact(L, false)>>2);
+    bgezalc(rt, shifted_branch_offset(L, false));
   }
   void bgezall(Register rs, int16_t offset);
   void bgezall(Register rs, Label* L) {
     bgezall(rs, branch_offset(L, false)>>2);
   }
   void bgtz(Register rs, int16_t offset);
   void bgtzc(Register rt, int16_t offset);
   void bgtzc(Register rt, Label* L) {
-    bgtzc(rt, branch_offset_compact(L, false)>>2);
+    bgtzc(rt, shifted_branch_offset(L, false));
   }
   void blez(Register rs, int16_t offset);
   void blezc(Register rt, int16_t offset);
   void blezc(Register rt, Label* L) {
-    blezc(rt, branch_offset_compact(L, false)>>2);
+    blezc(rt, shifted_branch_offset(L, false));
   }
   void bltz(Register rs, int16_t offset);
   void bltzc(Register rt, int16_t offset);
   void bltzc(Register rt, Label* L) {
-    bltzc(rt, branch_offset_compact(L, false)>>2);
+    bltzc(rt, shifted_branch_offset(L, false));
   }
   void bltuc(Register rs, Register rt, int16_t offset);
   void bltuc(Register rs, Register rt, Label* L) {
-    bltuc(rs, rt, branch_offset_compact(L, false)>>2);
+    bltuc(rs, rt, shifted_branch_offset(L, false));
   }
   void bltc(Register rs, Register rt, int16_t offset);
   void bltc(Register rs, Register rt, Label* L) {
-    bltc(rs, rt, branch_offset_compact(L, false)>>2);
+    bltc(rs, rt, shifted_branch_offset(L, false));
   }
   void bltzal(Register rs, int16_t offset);
   void blezalc(Register rt, int16_t offset);
   void blezalc(Register rt, Label* L) {
-    blezalc(rt, branch_offset_compact(L, false)>>2);
+    blezalc(rt, shifted_branch_offset(L, false));
   }
   void bltzalc(Register rt, int16_t offset);
   void bltzalc(Register rt, Label* L) {
-    bltzalc(rt, branch_offset_compact(L, false)>>2);
+    bltzalc(rt, shifted_branch_offset(L, false));
   }
   void bgtzalc(Register rt, int16_t offset);
   void bgtzalc(Register rt, Label* L) {
-    bgtzalc(rt, branch_offset_compact(L, false)>>2);
+    bgtzalc(rt, shifted_branch_offset(L, false));
   }
   void beqzalc(Register rt, int16_t offset);
   void beqzalc(Register rt, Label* L) {
-    beqzalc(rt, branch_offset_compact(L, false)>>2);
+    beqzalc(rt, shifted_branch_offset(L, false));
   }
   void beqc(Register rs, Register rt, int16_t offset);
   void beqc(Register rs, Register rt, Label* L) {
-    beqc(rs, rt, branch_offset_compact(L, false)>>2);
+    beqc(rs, rt, shifted_branch_offset(L, false));
   }
   void beqzc(Register rs, int32_t offset);
   void beqzc(Register rs, Label* L) {
-    beqzc(rs, branch_offset21_compact(L, false)>>2);
+    beqzc(rs, shifted_branch_offset21(L, false));
   }
   void bnezalc(Register rt, int16_t offset);
   void bnezalc(Register rt, Label* L) {
-    bnezalc(rt, branch_offset_compact(L, false)>>2);
+    bnezalc(rt, shifted_branch_offset(L, false));
   }
   void bnec(Register rs, Register rt, int16_t offset);
   void bnec(Register rs, Register rt, Label* L) {
-    bnec(rs, rt, branch_offset_compact(L, false)>>2);
+    bnec(rs, rt, shifted_branch_offset(L, false));
   }
   void bnezc(Register rt, int32_t offset);
   void bnezc(Register rt, Label* L) {
-    bnezc(rt, branch_offset21_compact(L, false)>>2);
+    bnezc(rt, shifted_branch_offset21(L, false));
   }
   void bne(Register rs, Register rt, int16_t offset);
   void bne(Register rs, Register rt, Label* L) {
-    bne(rs, rt, branch_offset(L, false)>>2);
+    bne(rs, rt, shifted_branch_offset(L, false));
   }
   void bovc(Register rs, Register rt, int16_t offset);
   void bovc(Register rs, Register rt, Label* L) {
-    bovc(rs, rt, branch_offset_compact(L, false)>>2);
+    bovc(rs, rt, shifted_branch_offset(L, false));
   }
   void bnvc(Register rs, Register rt, int16_t offset);
   void bnvc(Register rs, Register rt, Label* L) {
-    bnvc(rs, rt, branch_offset_compact(L, false)>>2);
+    bnvc(rs, rt, shifted_branch_offset(L, false));
   }
 
   // Never use the int16_t b(l)cond version with a branch offset
   // instead of using the Label* version.
 
   // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits.
   void j(int32_t target);
   void jal(int32_t target);
   void jalr(Register rs, Register rd = ra);
   void jr(Register target);
@@ skipping 225 matching lines @@
   void cvt_d_s(FPURegister fd, FPURegister fs);
 
   // Conditions and branches for MIPSr6.
   void cmp(FPUCondition cond, SecondaryField fmt,
          FPURegister fd, FPURegister ft, FPURegister fs);
   void cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft);
   void cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft);
 
   void bc1eqz(int16_t offset, FPURegister ft);
   void bc1eqz(Label* L, FPURegister ft) {
-    bc1eqz(branch_offset(L, false)>>2, ft);
+    bc1eqz(shifted_branch_offset(L, false), ft);
   }
   void bc1nez(int16_t offset, FPURegister ft);
   void bc1nez(Label* L, FPURegister ft) {
-    bc1nez(branch_offset(L, false)>>2, ft);
+    bc1nez(shifted_branch_offset(L, false), ft);
   }
 
   // Conditions and branches for non MIPSr6.
   void c(FPUCondition cond, SecondaryField fmt,
          FPURegister ft, FPURegister fs, uint16_t cc = 0);
   void c_s(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0);
   void c_d(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0);
 
   void bc1f(int16_t offset, uint16_t cc = 0);
-  void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); }
+  void bc1f(Label* L, uint16_t cc = 0) {
+    bc1f(shifted_branch_offset(L, false), cc);
+  }
   void bc1t(int16_t offset, uint16_t cc = 0);
-  void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); }
+  void bc1t(Label* L, uint16_t cc = 0) {
+    bc1t(shifted_branch_offset(L, false), cc);
+  }
   void fcmp(FPURegister src1, const double src2, FPUCondition cond);
 
   // Check the code size generated from label to here.
   int SizeOfCodeGeneratedSince(Label* label) {
     return pc_offset() - label->pos();
   }
 
   // Check the number of instructions generated from label to here.
   int InstructionsGeneratedSince(Label* label) {
     return SizeOfCodeGeneratedSince(label) / kInstrSize;
@@ skipping 98 matching lines @@
   static void instr_at_put(byte* pc, Instr instr) {
     *reinterpret_cast<Instr*>(pc) = instr;
   }
   Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
   void instr_at_put(int pos, Instr instr) {
     *reinterpret_cast<Instr*>(buffer_ + pos) = instr;
   }
 
   // Check if an instruction is a branch of some kind.
   static bool IsBranch(Instr instr);
+  static bool IsBc(Instr instr);
+  static bool IsBzc(Instr instr);
   static bool IsBeq(Instr instr);
   static bool IsBne(Instr instr);
+  static bool IsBeqzc(Instr instr);
+  static bool IsBnezc(Instr instr);
+  static bool IsBeqc(Instr instr);
+  static bool IsBnec(Instr instr);
 
   static bool IsJump(Instr instr);
   static bool IsJ(Instr instr);
   static bool IsLui(Instr instr);
   static bool IsOri(Instr instr);
 
   static bool IsJal(Instr instr);
   static bool IsJr(Instr instr);
   static bool IsJalr(Instr instr);
 
@@ skipping 101 matching lines @@
 
   void EndBlockGrowBuffer() {
     DCHECK(block_buffer_growth_);
     block_buffer_growth_ = false;
   }
 
   bool is_buffer_growth_blocked() const {
     return block_buffer_growth_;
   }
 
+  bool IsPrevInstrCompactBranch() { return prev_instr_compact_branch_; }
+
  private:
   inline static void set_target_internal_reference_encoded_at(Address pc,
                                                               Address target);
 
   // Buffer size and constant pool distance are checked together at regular
   // intervals of kBufferCheckInterval emitted bytes.
   static const int kBufferCheckInterval = 1*KB/2;
 
   // Code generation.
   // The relocation writer's position is at least kGap bytes below the end of
@@ skipping 166 matching lines @@
   int32_t get_trampoline_entry(int32_t pos);
   int unbound_labels_count_;
   // If trampoline is emitted, generated code is becoming large. As this is
   // already a slow case which can possibly break our code generation for the
   // extreme case, we use this information to trigger different mode of
   // branch instruction generation, where we use jump instructions rather
   // than regular branch instructions.
   bool trampoline_emitted_;
   static const int kTrampolineSlotsSize = 4 * kInstrSize;
   static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
+  static const int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1;
   static const int kInvalidSlotPos = -1;
 
   // Internal reference positions, required for unbounded internal reference
   // labels.
   std::set<int> internal_reference_positions_;
 
+  void EmittedCompactBranchInstruction() { prev_instr_compact_branch_ = true; }

[ivica.bogosavljevic, 2015/10/15 11:49:08]

The names of the functions EmittedCompactBranchInstruction and should be paired
for clarity ClearCompactBranchState, example:
MarkCompactBranchInstructionEmitted
ClearCompactBranchInstructionEmitted

[balazs.kilvady, 2015/10/30 21:11:14]

I don't agree, please discuss it with Paul.

+  void ClearCompactBranchState() { prev_instr_compact_branch_ = false; }
+  bool prev_instr_compact_branch_ = false;
+
   Trampoline trampoline_;
   bool internal_trampoline_exception_;
 
   friend class RegExpMacroAssemblerMIPS;
   friend class RelocInfo;
   friend class CodePatcher;
   friend class BlockTrampolinePoolScope;
 
   PositionsRecorder positions_recorder_;
   friend class PositionsRecorder;
   friend class EnsureSpace;
 };
 
 
 class EnsureSpace BASE_EMBEDDED {
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM_ASSEMBLER_MIPS_H_