Use generated actual decoders for ARM table:

src/trusted/validator_arm/gen/arm32_decode_baselines_1.h

Index: src/trusted/validator_arm/gen/arm32_decode_baselines_1.h
===================================================================
--- src/trusted/validator_arm/gen/arm32_decode_baselines_1.h	(revision 10736)
+++ src/trusted/validator_arm/gen/arm32_decode_baselines_1.h	(working copy)
@@ -837,6 +837,7 @@
 //   {Cond: Cond(31:28),
 //    Lr: 14,
 //    Pc: 15,
+//    actual: Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1,
 //    baseline: BranchImmediate24,
 //    constraints: ,
 //    defs: {Pc, Lr},
@@ -846,7 +847,7 @@
 //    imm32: SignExtend(imm24:'00'(1:0), 32),
 //    pattern: cccc1011iiiiiiiiiiiiiiiiiiiiiiii,
 //    relative: true,
-//    relative_offset: imm32,
+//    relative_offset: imm32 + 8,
 //    rule: BL_BLX_immediate,
 //    safety: [true => MAY_BE_SAFE],
 //    true: true,
@@ -870,6 +871,7 @@
 //
 //   {Cond: Cond(31:28),
 //    Pc: 15,
+//    actual: Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1,
 //    baseline: BranchImmediate24,
 //    constraints: ,
 //    defs: {Pc},
@@ -879,7 +881,7 @@
 //    imm32: SignExtend(imm24:'00'(1:0), 32),
 //    pattern: cccc1010iiiiiiiiiiiiiiiiiiiiiiii,
 //    relative: true,
-//    relative_offset: imm32,
+//    relative_offset: imm32 + 8,
 //    rule: B,
 //    safety: [true => MAY_BE_SAFE],
 //    true: true,
@@ -1625,6 +1627,7 @@
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
@@ -1645,8 +1648,7 @@
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 class LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0
@@ -1671,6 +1673,7 @@
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
@@ -1691,8 +1694,7 @@
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 class LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0
@@ -1717,6 +1719,7 @@
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
@@ -1737,8 +1740,7 @@
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 class LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0
@@ -1763,6 +1765,7 @@
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
@@ -1783,8 +1786,7 @@
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 class LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0