Use generated actual decoders for ARM table:

src/trusted/validator_arm/gen/arm32_decode_baselines_1.h

 /*
  * Copyright 2013 The Native Client Authors.  All rights reserved.
  * Use of this source code is governed by a BSD-style license that can
  * be found in the LICENSE file.
  */
 
 // DO NOT EDIT: GENERATED CODE
 
 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_1_H_
 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_1_H_
@@ skipping 819 matching lines @@
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       BLX_register_cccc000100101111111111110011mmmm_case_0);
 };
 
 // BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0:
 //
 //   {Cond: Cond(31:28),
 //    Lr: 14,
 //    Pc: 15,
+//    actual: Actual_BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_1,
 //    baseline: BranchImmediate24,
 //    constraints: ,
 //    defs: {Pc, Lr},
 //    fields: [Cond(31:28), imm24(23:0)],
 //    generated_baseline: BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0,
 //    imm24: imm24(23:0),
 //    imm32: SignExtend(imm24:'00'(1:0), 32),
 //    pattern: cccc1011iiiiiiiiiiiiiiiiiiiiiiii,
 //    relative: true,
-//    relative_offset: imm32,
+//    relative_offset: imm32 + 8,
 //    rule: BL_BLX_immediate,
 //    safety: [true => MAY_BE_SAFE],
 //    true: true,
 //    uses: {Pc}}
 class BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0
      : public ClassDecoder {
  public:
   BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0()
      : ClassDecoder() {}
   virtual RegisterList defs(Instruction inst) const;
   virtual bool is_relative_branch(Instruction i) const;
   virtual int32_t branch_target_offset(Instruction i) const;
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0);
 };
 
 // B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0:
 //
 //   {Cond: Cond(31:28),
 //    Pc: 15,
+//    actual: Actual_B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_1,
 //    baseline: BranchImmediate24,
 //    constraints: ,
 //    defs: {Pc},
 //    fields: [Cond(31:28), imm24(23:0)],
 //    generated_baseline: B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0,
 //    imm24: imm24(23:0),
 //    imm32: SignExtend(imm24:'00'(1:0), 32),
 //    pattern: cccc1010iiiiiiiiiiiiiiiiiiiiiiii,
 //    relative: true,
-//    relative_offset: imm32,
+//    relative_offset: imm32 + 8,
 //    rule: B,
 //    safety: [true => MAY_BE_SAFE],
 //    true: true,
 //    uses: {Pc}}
 class B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0
      : public ClassDecoder {
  public:
   B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0()
      : ClassDecoder() {}
   virtual RegisterList defs(Instruction inst) const;
@@ skipping 725 matching lines @@
   NACL_DISALLOW_COPY_AND_ASSIGN(
       LDC_literal_cccc110pudw11111ddddcccciiiiiiii_case_0);
 };
 
 // LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: Union({Rn
 //         if wback
 //         else None}, registers),
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100000w1nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: LDMDA_LDMFA,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 class LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0
      : public ClassDecoder {
  public:
   LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0()
      : ClassDecoder() {}
   virtual Register base_address_register(Instruction i) const;
   virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
   virtual bool base_address_register_writeback_small_immediate(
       Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0);
 };
 
 // LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: Union({Rn
 //         if wback
 //         else None}, registers),
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100100w1nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: LDMDB_LDMEA,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 class LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0
      : public ClassDecoder {
  public:
   LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0()
      : ClassDecoder() {}
   virtual Register base_address_register(Instruction i) const;
   virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
   virtual bool base_address_register_writeback_small_immediate(
       Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0);
 };
 
 // LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: Union({Rn
 //         if wback
 //         else None}, registers),
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100110w1nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: LDMIB_LDMED,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 class LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0
      : public ClassDecoder {
  public:
   LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0()
      : ClassDecoder() {}
   virtual Register base_address_register(Instruction i) const;
   virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
   virtual bool base_address_register_writeback_small_immediate(
       Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0);
 };
 
 // LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0:
 //
 //   {None: 32,
 //    Pc: 15,
 //    Rn: Rn(19:16),
 //    W: W(21),
+//    actual: Actual_LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_1,
 //    base: Rn,
 //    baseline: LoadRegisterList,
 //    cond: cond(31:28),
 //    constraints: ,
 //    defs: Union({Rn
 //         if wback
 //         else None}, registers),
 //    fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)],
 //    generated_baseline: LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0,
 //    pattern: cccc100010w1nnnnrrrrrrrrrrrrrrrr,
 //    register_list: register_list(15:0),
 //    registers: RegisterList(register_list),
 //    rule: LDM_LDMIA_LDMFD,
 //    safety: [Rn  ==
 //            Pc ||
 //         NumGPRs(registers)  <
 //            1 => UNPREDICTABLE,
 //      wback &&
 //         Contains(registers, Rn) => UNKNOWN,
 //      Contains(registers, Pc) => FORBIDDEN_OPERANDS],
-//    small_imm_base_wb: true,
-//    true: true,
+//    small_imm_base_wb: wback,
 //    uses: {Rn},
 //    wback: W(21)=1}
 class LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0
      : public ClassDecoder {
  public:
   LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0()
      : ClassDecoder() {}
   virtual Register base_address_register(Instruction i) const;
   virtual RegisterList defs(Instruction inst) const;
   virtual SafetyLevel safety(Instruction i) const;
@@ skipping 4265 matching lines @@
   virtual SafetyLevel safety(Instruction i) const;
   virtual RegisterList uses(Instruction i) const;
  private:
   NACL_DISALLOW_COPY_AND_ASSIGN(
       SMLSLD_cccc01110100hhhhllllmmmm01m1nnnn_case_0);
 };
 
 } // namespace nacl_arm_test
 
 #endif  // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_1_H_