Subzero: Add -Wshadow to the build.

src/IceTargetLoweringARM32.cpp

Index: src/IceTargetLoweringARM32.cpp
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 10fdfe12a1b4a6f7c1b9a6bb334caa0e5d8530bb..1b53b9f543979fa192d7c0f7dc1e4df4ae8ab9e2 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -27,7 +27,12 @@
 #include "IceRegistersARM32.h"
 #include "IceTargetLoweringARM32.def"
 #include "IceUtils.h"
+
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wunused-parameter"
+#pragma clang diagnostic ignored "-Wshadow"
 #include "llvm/Support/MathExtras.h"
+#pragma clang diagnostic pop
 
 namespace Ice {
 
@@ -1262,7 +1267,6 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
       // On ARM, shifts only take the lower 8 bits of the shift register,
       // and saturate to the range 0-32, so the negative value will
       // saturate to 32.
-      Variable *T_Hi = makeReg(IceType_i32);
       Variable *Src1RLo = legalizeToVar(Src1Lo);
       Constant *ThirtyTwo = Ctx->getConstantInt32(32);
       Variable *T_C1 = makeReg(IceType_i32);
@@ -1275,7 +1279,6 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
       _orr(T_Hi, T_Hi, OperandARM32FlexReg::create(Func, IceType_i32, Src0RLo,
                                                    OperandARM32::LSR, T_C2));
       _mov(DestHi, T_Hi);
-      Variable *T_Lo = makeReg(IceType_i32);
       // _mov seems to sometimes have better register preferencing than lsl.
       // Otherwise mov w/ lsl shifted register is a pseudo-instruction
       // that maps to lsl.
@@ -1301,7 +1304,6 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
       // and the next orr should be conditioned on PLUS. The last two
       // right shifts should also be arithmetic.
       bool IsAshr = Inst->getOp() == InstArithmetic::Ashr;
-      Variable *T_Lo = makeReg(IceType_i32);
       Variable *Src1RLo = legalizeToVar(Src1Lo);
       Constant *ThirtyTwo = Ctx->getConstantInt32(32);
       Variable *T_C1 = makeReg(IceType_i32);
@@ -1325,7 +1327,6 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
                                                    RShiftKind, T_C2),
            Pred);
       _mov(DestLo, T_Lo);
-      Variable *T_Hi = makeReg(IceType_i32);
       _mov(T_Hi, OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
                                              RShiftKind, Src1RLo));
       _mov(DestHi, T_Hi);
@@ -1662,7 +1663,6 @@ void TargetARM32::lowerCall(const InstCall *Instr) {
   if (ParameterAreaSizeBytes) {
     Operand *AddAmount = legalize(Ctx->getConstantInt32(ParameterAreaSizeBytes),
                                   Legal_Reg | Legal_Flex);
-    Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
     _add(SP, SP, AddAmount);
   }
 
@@ -1808,7 +1808,6 @@ void TargetARM32::lowerCast(const InstCast *Inst) {
     if (isVectorType(Dest->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
     } else {
-      Operand *Src0 = Inst->getSrc(0);
       if (Src0->getType() == IceType_i64)
         Src0 = loOperand(Src0);
       Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
@@ -1842,7 +1841,6 @@ void TargetARM32::lowerCast(const InstCast *Inst) {
     break;
   }
   case InstCast::Bitcast: {
-    Operand *Src0 = Inst->getSrc(0);
     if (Dest->getType() == Src0->getType()) {
       InstAssign *Assign = InstAssign::create(Func, Dest, Src0);
       lowerAssign(Assign);