Subzero: Add -Wshadow to the build.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file implements the TargetLoweringARM32 class, which consists almost
 /// entirely of the lowering sequence for each high-level instruction.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "IceTargetLoweringARM32.h"
 
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceClFlags.h"
 #include "IceDefs.h"
 #include "IceELFObjectWriter.h"
 #include "IceGlobalInits.h"
 #include "IceInstARM32.h"
 #include "IceLiveness.h"
 #include "IceOperand.h"
 #include "IceRegistersARM32.h"
 #include "IceTargetLoweringARM32.def"
 #include "IceUtils.h"
+
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wunused-parameter"
+#pragma clang diagnostic ignored "-Wshadow"
 #include "llvm/Support/MathExtras.h"
+#pragma clang diagnostic pop
 
 namespace Ice {
 
 namespace {
 
 void UnimplementedError(const ClFlags &Flags) {
   if (!Flags.getSkipUnimplemented()) {
     // Use llvm_unreachable instead of report_fatal_error, which gives better
     // stack traces.
     llvm_unreachable("Not yet implemented");
@@ skipping 1214 matching lines @@
       // orr t_hi, t_hi, b.lo, lsr t_c2
       // lsl t_lo, b.lo, c.lo
       // a.lo = t_lo
       // a.hi = t_hi
       // Can be strength-reduced for constant-shifts, but we don't do
       // that for now.
       // Given the sub/rsb T_C, C.lo, #32, one of the T_C will be negative.
       // On ARM, shifts only take the lower 8 bits of the shift register,
       // and saturate to the range 0-32, so the negative value will
       // saturate to 32.
-      Variable *T_Hi = makeReg(IceType_i32);
       Variable *Src1RLo = legalizeToVar(Src1Lo);
       Constant *ThirtyTwo = Ctx->getConstantInt32(32);
       Variable *T_C1 = makeReg(IceType_i32);
       Variable *T_C2 = makeReg(IceType_i32);
       _sub(T_C1, Src1RLo, ThirtyTwo);
       _lsl(T_Hi, Src0RHi, Src1RLo);
       _orr(T_Hi, T_Hi, OperandARM32FlexReg::create(Func, IceType_i32, Src0RLo,
                                                    OperandARM32::LSL, T_C1));
       _rsb(T_C2, Src1RLo, ThirtyTwo);
       _orr(T_Hi, T_Hi, OperandARM32FlexReg::create(Func, IceType_i32, Src0RLo,
                                                    OperandARM32::LSR, T_C2));
       _mov(DestHi, T_Hi);
-      Variable *T_Lo = makeReg(IceType_i32);
       // _mov seems to sometimes have better register preferencing than lsl.
       // Otherwise mov w/ lsl shifted register is a pseudo-instruction
       // that maps to lsl.
       _mov(T_Lo, OperandARM32FlexReg::create(Func, IceType_i32, Src0RLo,
                                              OperandARM32::LSL, Src1RLo));
       _mov(DestLo, T_Lo);
       return;
     }
     case InstArithmetic::Lshr:
     // a=b>>c (unsigned) ==>
     // GCC 4.8 does:
     // rsb t_c1, c.lo, #32
     // lsr t_lo, b.lo, c.lo
     // orr t_lo, t_lo, b.hi, lsl t_c1
     // sub t_c2, c.lo, #32
     // orr t_lo, t_lo, b.hi, lsr t_c2
     // lsr t_hi, b.hi, c.lo
     // a.lo = t_lo
     // a.hi = t_hi
     case InstArithmetic::Ashr: {
       // a=b>>c (signed) ==> ...
       // Ashr is similar, but the sub t_c2, c.lo, #32 should set flags,
       // and the next orr should be conditioned on PLUS. The last two
       // right shifts should also be arithmetic.
       bool IsAshr = Inst->getOp() == InstArithmetic::Ashr;
-      Variable *T_Lo = makeReg(IceType_i32);
       Variable *Src1RLo = legalizeToVar(Src1Lo);
       Constant *ThirtyTwo = Ctx->getConstantInt32(32);
       Variable *T_C1 = makeReg(IceType_i32);
       Variable *T_C2 = makeReg(IceType_i32);
       _rsb(T_C1, Src1RLo, ThirtyTwo);
       _lsr(T_Lo, Src0RLo, Src1RLo);
       _orr(T_Lo, T_Lo, OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
                                                    OperandARM32::LSL, T_C1));
       OperandARM32::ShiftKind RShiftKind;
       CondARM32::Cond Pred;
       if (IsAshr) {
         _subs(T_C2, Src1RLo, ThirtyTwo);
         RShiftKind = OperandARM32::ASR;
         Pred = CondARM32::PL;
       } else {
         _sub(T_C2, Src1RLo, ThirtyTwo);
         RShiftKind = OperandARM32::LSR;
         Pred = CondARM32::AL;
       }
       _orr(T_Lo, T_Lo, OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
                                                    RShiftKind, T_C2),
            Pred);
       _mov(DestLo, T_Lo);
-      Variable *T_Hi = makeReg(IceType_i32);
       _mov(T_Hi, OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
                                              RShiftKind, Src1RLo));
       _mov(DestHi, T_Hi);
       return;
     }
     case InstArithmetic::Fadd:
     case InstArithmetic::Fsub:
     case InstArithmetic::Fmul:
     case InstArithmetic::Fdiv:
     case InstArithmetic::Frem:
@@ skipping 316 matching lines @@
   Inst *NewCall = InstARM32Call::create(Func, ReturnReg, CallTarget);
   Context.insert(NewCall);
   if (ReturnRegHi)
     Context.insert(InstFakeDef::create(Func, ReturnRegHi));
 
   // Add the appropriate offset to SP.  The call instruction takes care
   // of resetting the stack offset during emission.
   if (ParameterAreaSizeBytes) {
     Operand *AddAmount = legalize(Ctx->getConstantInt32(ParameterAreaSizeBytes),
                                   Legal_Reg | Legal_Flex);
-    Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
     _add(SP, SP, AddAmount);
   }
 
   // Insert a register-kill pseudo instruction.
   Context.insert(InstFakeKill::create(Func, NewCall));
 
   // Generate a FakeUse to keep the call live if necessary.
   if (Instr->hasSideEffects() && ReturnReg) {
     Inst *FakeUse = InstFakeUse::create(Func, ReturnReg);
     Context.insert(FakeUse);
@@ skipping 125 matching lines @@
       Variable *T = makeReg(Dest->getType());
       _uxt(T, Src0R);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Trunc: {
     if (isVectorType(Dest->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
     } else {
-      Operand *Src0 = Inst->getSrc(0);
       if (Src0->getType() == IceType_i64)
         Src0 = loOperand(Src0);
       Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
       // t1 = trunc Src0RF; Dest = t1
       Variable *T = makeReg(Dest->getType());
       _mov(T, Src0RF);
       if (Dest->getType() == IceType_i1)
         _and(T, T, Ctx->getConstantInt1(1));
       _mov(Dest, T);
     }
@@ skipping 13 matching lines @@
     UnimplementedError(Func->getContext()->getFlags());
     break;
   case InstCast::Sitofp:
     UnimplementedError(Func->getContext()->getFlags());
     break;
   case InstCast::Uitofp: {
     UnimplementedError(Func->getContext()->getFlags());
     break;
   }
   case InstCast::Bitcast: {
-    Operand *Src0 = Inst->getSrc(0);
     if (Dest->getType() == Src0->getType()) {
       InstAssign *Assign = InstAssign::create(Func, Dest, Src0);
       lowerAssign(Assign);
       return;
     }
     UnimplementedError(Func->getContext()->getFlags());
     break;
   }
   }
 }
@@ skipping 890 matching lines @@
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
     Str << ".eabi_attribute 44, 2   @ Tag_DIV_use\n";
   }
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 } // end of namespace Ice