Subzero: Transform suitable Load/Arith/Store sequences into RMW ops.

src/IceAssemblerX8632.cpp

Index: src/IceAssemblerX8632.cpp
diff --git a/src/IceAssemblerX8632.cpp b/src/IceAssemblerX8632.cpp
index a45e7cc813030ad39de35b9229f69ffbdab1310a..48f023c16fe93ad867b84eb23d49b8483a1d9c92 100644
--- a/src/IceAssemblerX8632.cpp
+++ b/src/IceAssemblerX8632.cpp
@@ -1759,6 +1759,29 @@ void AssemblerX8632::add(Type Ty, GPRRegister reg, const Immediate &imm) {
   emitComplex(Ty, 0, Operand(reg), imm);
 }
 
+void AssemblerX8632::add(Type Ty, const Address &address, GPRRegister reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  if (Ty == IceType_i16)
+    emitOperandSizeOverride();
+  if (isByteSizedArithType(Ty))
+    emitUint8(0x00);
+  else
+    emitUint8(0x01);
+  emitOperand(reg, address);
+}
+
+void AssemblerX8632::add(Type Ty, const Address &address,
+                         const Immediate &imm) {
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  if (isByteSizedArithType(Ty)) {
+    emitComplexI8(0, address, imm);
+    return;
+  }
+  if (Ty == IceType_i16)
+    emitOperandSizeOverride();
+  emitComplex(Ty, 0, address, imm);
+}
+
 void AssemblerX8632::adc(Type Ty, GPRRegister dst, GPRRegister src) {
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   if (Ty == IceType_i16)