src/trusted/validator_arm/testdata/test_loads.S - Issue 11348120: Remove tst+ldr, tst+str from checked-in nexes.

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Unified Diff: src/trusted/validator_arm/testdata/test_loads.S

Issue 11348120: Remove tst+ldr, tst+str from checked-in nexes. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client

Patch Set: Created 8 years, 1 month ago

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Index: src/trusted/validator_arm/testdata/test_loads.S

diff --git a/src/trusted/validator_arm/testdata/test_loads.S b/src/trusted/validator_arm/testdata/test_loads.S

index a6d34de7e8b1fcb4faa87163b780a269c869821d..24f3140a7f61c4c92a7a4f03124dd273b045a677 100644

--- a/src/trusted/validator_arm/testdata/test_loads.S

+++ b/src/trusted/validator_arm/testdata/test_loads.S

@@ -79,17 +79,3 @@ bundle9:

ldr r1, [sp], r2 @ post-indexing sp by a register is an ERROR

nop

-conditional_sandbox:

- tst r0, #0xC0000000 @ Set Z if the top two bits are clear, and

- ldreq r1, [r0] @ load: should work.

- tst r0, #0xC0000000 @ Set Z if the top two bits are clear, and

- ldr r1, [r0] @ load unconditionally: ERROR.

- tst r0, #0xC0000000 @ Set Z if the top two bits are clear, and

- ldrgt r1, [r0] @ load using wrong predicate: ERROR.

- tsteq r0, #0xC0000000 @ Conditionally set Z if the top two bits are clear,

- ldrgt r1, [r0] @ and load using wrong predicate: ERROR.

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