Remove tst+ldr, tst+str from checked-in nexes.

src/trusted/validator_arm/testdata/test_loads.S

 @ Copyright (c) 2011 The Native Client Authors. All rights reserved.
 @ Use of this source code is governed by a BSD-style license that can be
 @ found in the LICENSE file.
 
 @
 @ Tests both legal and illegal variations on loads -- both loads that
 @ require masking, and loads that are guaranteed sandboxed (i.e. through SP)
 @
 
 @ we restrict loads to the lower 1GB of the address space
@@ skipping 61 matching lines @@
   ldr r1, [r1, r2]        @ loading with an index is an ERROR
 
   nop
   nop
 
 bundle9:
   ldr r1, [sp], #1024     @ post-indexing sp by a constant is fine.
   ldr r1, [sp], r2        @ post-indexing sp by a register is an ERROR
   nop
   nop
-
-
-conditional_sandbox:
-  tst r0, #0xC0000000     @ Set Z if the top two bits are clear, and
-  ldreq r1, [r0]          @ load: should work.
-
-  tst r0, #0xC0000000     @ Set Z if the top two bits are clear, and
-  ldr r1, [r0]            @ load unconditionally: ERROR.
-
-  tst r0, #0xC0000000     @ Set Z if the top two bits are clear, and
-  ldrgt r1, [r0]          @ load using wrong predicate: ERROR.
-
-  tsteq r0, #0xC0000000   @ Conditionally set Z if the top two bits are clear,
-  ldrgt r1, [r0]          @ and load using wrong predicate: ERROR.