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Issue
1127003003:
Lower a few basic ARM binops for i{8,16,32,64}. (Closed)
DescriptionLower a few basic ARM binops for i{8,16,32,64}.
Do basic lowering for add, sub, and, or, xor, mul.
We don't yet take advantage of commuting immediate operands
(e.g., use rsb to reverse subtract instead of sub) or
inverting immediate operands (use bic to bit clear instead
of using and).
The binary operations can set the flags register (e.g., to
have the carry bit for use with a subsequent adc
instruction). That is optional for the "data processing"
instructions.
I'm not yet able to compile 8bit.pnacl.ll and
64bit.pnacl.ll so 8-bit and 64-bit are not well tested yet.
Only tests are in the arith.ll file (like arith-opt.ll, but
assembled instead of testing the "verbose inst" output).
Not doing divide yet. ARM divide by 0 does not trap, but
PNaCl requires uniform behavior for such bad code. Thus,
in LLVM we insert a 0 check and would have to do the same.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=stichnot@chromium.org
Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=2971997a96b7484165cfedead111c7cafb3073ae
Patch Set 1 #Patch Set 2 : do 64-bit multiply also #Patch Set 3 : clang format #Patch Set 4 : remove unused rsb, rsc #
Total comments: 1
Patch Set 5 : stuff #Patch Set 6 : move comment #
Total comments: 2
Patch Set 7 : added condition and target to test #
Messages
Total messages: 5 (1 generated)
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