Revert MMIO space writes on shutdown as needed.

Revert MMIO space writes on shutdown as needed.

Basically this patch comes from http://patchwork.coreboot.org/patch/2331/
But fixed 2 bugs in original patch:
  program_opcodes(): should be rmmio_write"l"(..., ICH7_REG_OPMENU)
  undo_mmio_write():
    case mmio_write_type_w:
                mmio_write"w"(data->wdata, data->addr);
    case mmio_write_type_l:
                mmio_write"l"(data->ldata, data->addr);

Also add BBS register revert.

Change-Id: I28dfa5b4b970a4c28ddbd5e103e2cefadb4c2ab7

BUG=chromium-os:9586
TEST=Tested on Mario:
flashrom -V > 1
flashrom -V -p internal:bus=lpc > 2
flashrom -V > 3
flashrom -V -p internal:bus=spi > 4
flashrom -V > 5
grep Found 1 2 3 4 5
W25Q32  # bus=spi
W24X40  # bus=lpc
W25Q32  # bus=spi
W25Q32  # bus=spi
W25Q32  # bus=spi
Above results prove that the BBS register is restored (in step 2) and no side-effect.

Committed: http://chrome-svn/viewvc/chromeos?view=rev&revision=e6e628f

Committed: http://chrome-svn/viewvc/chromeos?view=rev&revision=cd93c97

[Stefan Reinauer, 2011-04-19 18:24:55]

Those comments are kind of weird. Otherwise
LGTM

http://codereview.chromium.org/6877037/diff/1006/nicintel_spi.c
File nicintel_spi.c (right):

http://codereview.chromium.org/6877037/diff/1006/nicintel_spi.c#newcode152
nicintel_spi.c:152: /* Automatic restore is not possible because we only change
two bits. */
Why are two bits not enough?

[Louis, 2011-04-20 00:43:54]

Thanks, Stefan. Please see my comment.

http://codereview.chromium.org/6877037/diff/1006/nicintel_spi.c
File nicintel_spi.c (right):

http://codereview.chromium.org/6877037/diff/1006/nicintel_spi.c#newcode152
nicintel_spi.c:152: /* Automatic restore is not possible because we only change
two bits. */
Hm.... I don't the exact reason, I just patch this from patchwork CL. I will
remove this before submit.

On 2011/04/19 18:24:55, Stefan Reinauer wrote:
> Why are two bits not enough?

[dhendrix, 2011-04-20 00:55:25]

LGTM. Thanks!

http://codereview.chromium.org/6877037/diff/1006/nicintel_spi.c
File nicintel_spi.c (right):

http://codereview.chromium.org/6877037/diff/1006/nicintel_spi.c#newcode152
nicintel_spi.c:152: /* Automatic restore is not possible because we only change
two bits. */
On 2011/04/20 00:43:55, Louis wrote:
> Hm.... I don't the exact reason, I just patch this from patchwork CL. I will
> remove this before submit.
> 
> On 2011/04/19 18:24:55, Stefan Reinauer wrote:
> > Why are two bits not enough?
> 

Agreed -- Removing the comment is probably best to avoid confusion. I believe
the author meant that restoring this register is simply a bad idea, since it
contains a lot of other SPI-related state (CLock, CS, MISO, MOSI) that should
only be set as-needed.

[Louis, 2011-04-29 09:37:11]

Re-submit this CL again since http://codereview.chromium.org/6897014/ has solved
the shutdown order issue. Thanks David and Stefan.

[Louis, 2011-04-29 09:38:20]

Note that, I have tested the patch on Alex, ZGB and Mario with following
commands:
    flashrom -V | grep Found: MX25L3205
    flashrom -V -p internal:bus=lpc | grep Found: MX25L1005
    flashrom -V | grep Found: MX25L3205
    flashrom -r -p internal:bus=spi -r /tmp/BIOS
    flashrom -r -p internal:bus=lpc -r /tmp/EC
    flashrom -r -r /tmp/BIOS2
    md5sum /tmp/BIOS*   # identical