Revert MMIO space writes on shutdown as needed.

nicintel_spi.c

 /*
  * This file is part of the flashrom project.
  *
  * Copyright (C) 2010 Carl-Daniel Hailfinger
  * Copyright (C) 2010 Idwer Vollering
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
  *
@@ skipping 131 matching lines @@
 {
         uint32_t tmp;
 
         get_io_perms();
 
         io_base_addr = pcidev_init(PCI_VENDOR_ID_INTEL, PCI_BASE_ADDRESS_0,
                                    nics_intel_spi);
 
         nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash",
                                   io_base_addr, 4096);
+        /* Automatic restore is not possible because we only change two bits. */

[Stefan Reinauer, 2011/04/19 18:24:55]

Why are two bits not enough?

[Louis, 2011/04/20 00:43:55]

Hm.... I don't the exact reason, I just patch this from patchwork CL. I will
remove this before submit.

On 2011/04/19 18:24:55, Stefan Reinauer wrote:

[dhendrix, 2011/04/20 00:55:25]

Agreed -- Removing the comment is probably best to avoid confusion. I believe
the author meant that restoring this register is simply a bad idea, since it
contains a lot of other SPI-related state (CLock, CS, MISO, MOSI) that should
only be set as-needed.

         tmp = pci_mmio_readl(nicintel_spibar + EECD);
         tmp &= ~FLASH_WRITES_DISABLED;
         tmp |= FLASH_WRITES_ENABLED;
         pci_mmio_writel(tmp, nicintel_spibar + EECD);
 
         /* 1 usec halfperiod delay for now. */
         if (bitbang_spi_init(&bitbang_spi_master_nicintel, 1))
                 return 1;
 
         buses_supported = CHIP_BUSTYPE_SPI;
         spi_controller = SPI_CONTROLLER_NICINTEL;
 
         return 0;
 }
 
 int nicintel_spi_shutdown(void)
 {
         uint32_t tmp;
 
+        /* Automatic restore is not possible because we only change two bits. */
         tmp = pci_mmio_readl(nicintel_spibar + EECD);
         tmp &= ~FLASH_WRITES_ENABLED;
         tmp |= FLASH_WRITES_DISABLED;
         pci_mmio_writel(tmp, nicintel_spibar + EECD);
 
         physunmap(nicintel_spibar, 4096);
         pci_cleanup(pacc);
         release_io_perms();
 
         return 0;
 }