Issue 1606019: Make binary op stubs in both r0-r1 and r1-r0 versions to reduce...

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Issue 1606019: Make binary op stubs in both r0-r1 and r1-r0 versions to reduce... (Closed)

Created:
10 years, 8 months ago by Erik Corry

Modified:
10 years, 8 months ago

Reviewers:
Søren Thygesen Gjesse

CC:
v8-dev

Base URL:
http://v8.googlecode.com/svn/branches/bleeding_edge/

Visibility:
Public.

Description

Make binary op stubs in both r0-r1 and r1-r0 versions to reduce register churn. Committed: http://code.google.com/p/v8/source/detail?r=4380

Patch Set 1 #

Patch Set 2 : '' #

Total comments: 5

Created: 10 years, 8 months ago

Download [raw] [tar.bz2]

	Unified diffs	Side-by-side diffs	Delta from patch set	Stats (+194 lines, -126 lines)			Patch
M	src/arm/codegen-arm.h	View		5 chunks	+29 lines, -5 lines	0 comments	Download
M	src/arm/codegen-arm.cc	View	1	24 chunks	+162 lines, -119 lines	5 comments	Download
M	src/arm/full-codegen-arm.cc	View		2 chunks	+2 lines, -2 lines	0 comments	Download
M	src/arm/simulator-arm.cc	View		1 chunk	+1 line, -0 lines	0 comments	Download

Messages

Total messages: 2 (0 generated)

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Søren Thygesen Gjesse

10 years, 8 months ago (2010-04-09 13:22:35 UTC) #2

LGTM

http://codereview.chromium.org/1606019/diff/5001/6001
File src/arm/codegen-arm.cc (right):

http://codereview.chromium.org/1606019/diff/5001/6001#newcode1014
src/arm/codegen-arm.cc:1014: // Move the rhs to r0.
Does this comment still hold?

http://codereview.chromium.org/1606019/diff/5001/6001#newcode6400
src/arm/codegen-arm.cc:6400: 
How about having scratch registers here as well, and then never use any explicit
register below?

  Register t0 = VirtualFrame::scratch0();
  Register t1 = ...
  ...

http://codereview.chromium.org/1606019/diff/5001/6001#newcode6413
src/arm/codegen-arm.cc:6413: // This code can't cope with other register
allocations yet.
Doesn't this assert apply for the GenericBinaryOpStub as a whole? If this move
it to the top.

http://codereview.chromium.org/1606019/diff/5001/6001#newcode6433
src/arm/codegen-arm.cc:6433: // This code can't cope with other register
allocations yet.
Ditto.

http://codereview.chromium.org/1606019/diff/5001/6001#newcode6439
src/arm/codegen-arm.cc:6439: if (lhs.is(r1)) {
Can't you just drop the if/else and use:

__ sub(r0, lhs, Operand(rhs), SetCC);
// Return if no overflow.
__ Ret(vc);
__ sub(r0, lhs, Operand(rhs));  // Revert optimistic subtract.

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