Fix cases where fast instruction selection generated both base and index registers

llvm/lib/Target/X86/X86FastISel.cpp

Index: llvm/lib/Target/X86/X86FastISel.cpp
===================================================================
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -578,6 +578,20 @@
 
   // If all else fails, try to materialize the value in a register.
   if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
+    // @LOCALMOD-START
+    if (Subtarget->isTargetNaCl()) {
+      // We can materialize into a memory address only if
+      // no registers have been defined (and hence, we
+      // aren't modifying an existing memory reference).
+      if ((AM.Base.Reg == 0) && (AM.IndexReg == 0)) {
+        // Put into index register so that the NaCl rewrite pass will
+        // convert this to a 64-bit address.
+        AM.IndexReg = getRegForValue(V);
+        return AM.IndexReg != 0;
+      }
+      return false;
+    }
+    // @LOCALMOD-END
     if (AM.Base.Reg == 0) {
       AM.Base.Reg = getRegForValue(V);
       return AM.Base.Reg != 0;