Fix cases where fast instruction selection generated both base and index registers

llvm/lib/Target/X86/X86FastISel.cpp

 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the X86-specific support for the FastISel class. Much
@@ skipping 560 matching lines @@
       // Now construct the final address. Note that the Disp, Scale,
       // and Index values may already be set here.
       AM.Base.Reg = LoadReg;
       AM.GV = 0;
       return true;
     }
   }
 
   // If all else fails, try to materialize the value in a register.
   if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
+    // @LOCALMOD-START
+    if (Subtarget->isTargetNaCl()) {
+      // We can materialize into a memory address only if
+      // no registers have been defined (and hence, we
+      // aren't modifying an existing memory reference).
+      if ((AM.Base.Reg == 0) && (AM.IndexReg == 0)) {
+        // Put into index register so that the NaCl rewrite pass will
+        // convert this to a 64-bit address.
+        AM.IndexReg = getRegForValue(V);
+        return AM.IndexReg != 0;
+      }
+      return false;
+    }
+    // @LOCALMOD-END
     if (AM.Base.Reg == 0) {
       AM.Base.Reg = getRegForValue(V);
       return AM.Base.Reg != 0;
     }
     if (AM.IndexReg == 0) {
       assert(AM.Scale == 1 && "Scale with no index!");
       AM.IndexReg = getRegForValue(V);
       return AM.IndexReg != 0;
     }
   }
@@ skipping 1609 matching lines @@
   MI->eraseFromParent();
   return true;
 }
 
 
 namespace llvm {
   FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo) {
     return new X86FastISel(funcInfo);
   }
 }