Use a different variant of CpuFeatures::FlushICache asm with clang.

src/arm/cpu-arm.cc

Index: src/arm/cpu-arm.cc
diff --git a/src/arm/cpu-arm.cc b/src/arm/cpu-arm.cc
index 4a340708f9334faa7a59d127e9518067beca85e4..4bbfd375a8bd2465d1433c89e7163d45086e6489 100644
--- a/src/arm/cpu-arm.cc
+++ b/src/arm/cpu-arm.cc
@@ -45,6 +45,18 @@ void CpuFeatures::FlushICache(void* start, size_t size) {
   register uint32_t end asm("r1") = beg + size;
   register uint32_t flg asm("r2") = 0;
 
+#ifdef __clang__
+  // This variant of the asm avoids a constant pool entry, which can be
+  // problematic when LTO'ing. It is also slightly shorter.
+  register uint32_t scno asm("r7") = __ARM_NR_cacheflush;

[bnoordhuis, 2015/03/07 18:34:49]

I don't think it's safe to assume that the compiler will actually load the value
into the register this way.

A peephole optimizer can't see into the asm block and won't realize that the
register is actually used.  It may opt to remove the load.

[pcc1, 2015/03/07 21:26:39]

Please see https://gcc.gnu.org/onlinedocs/gcc/Local-Reg-Vars.html#Local-Reg-Vars
:

"However, using the variable as an input or output operand to the asm guarantees
that the specified register is used for that operand."

Note also that r0, r1, r2 are already being set in the same way. (Clang has the
same inline asm semantics as GCC, so it works the same way.)

+
+  asm volatile("svc 0\n"
+               :
+               : "r"(beg), "r"(end), "r"(flg), "r"(scno)
+               : "memory");
+#else
+  // Use a different variant of the asm with GCC because some versions doesn't
+  // support r7 as an asm input.
   asm volatile(
     // This assembly works for both ARM and Thumb targets.
 
@@ -62,6 +74,7 @@ void CpuFeatures::FlushICache(void* start, size_t size) {
     : "r" (beg), "r" (end), "r" (flg), [scno] "i" (__ARM_NR_cacheflush)
     : "memory");
 #endif
+#endif
 }
 
 } }  // namespace v8::internal