Index: src/mips64/simulator-mips64.cc |
diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc |
index 95b9fce7fc34a055abf95da695b024a8613847d7..5ddad8d5b4651214b96f69e1dbf435cdefea0a80 100644 |
--- a/src/mips64/simulator-mips64.cc |
+++ b/src/mips64/simulator-mips64.cc |
@@ -2045,7 +2045,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr, |
// Logical right-rotate of a word by a variable number of bits. |
// This is special case od SRLV instruction, added in MIPS32 |
// Release 2. SA field is equal to 00001. |
- *alu_out = base::bits::RotateRight32(((uint32_t)rt_u, rs_u); |
+ *alu_out = base::bits::RotateRight32((uint32_t)rt_u, rs_u); |
} |
break; |
case DSRLV: |