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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> | 5 #include <limits.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdlib.h> | 7 #include <stdlib.h> |
8 #include <cmath> | 8 #include <cmath> |
9 | 9 |
10 #include "src/v8.h" | 10 #include "src/v8.h" |
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2038 break; | 2038 break; |
2039 case SRLV: | 2039 case SRLV: |
2040 if (sa == 0) { | 2040 if (sa == 0) { |
2041 // Regular logical right-shift of a word by a variable number of | 2041 // Regular logical right-shift of a word by a variable number of |
2042 // bits instruction. SA field is always equal to 0. | 2042 // bits instruction. SA field is always equal to 0. |
2043 *alu_out = (uint32_t)rt_u >> rs; | 2043 *alu_out = (uint32_t)rt_u >> rs; |
2044 } else { | 2044 } else { |
2045 // Logical right-rotate of a word by a variable number of bits. | 2045 // Logical right-rotate of a word by a variable number of bits. |
2046 // This is special case od SRLV instruction, added in MIPS32 | 2046 // This is special case od SRLV instruction, added in MIPS32 |
2047 // Release 2. SA field is equal to 00001. | 2047 // Release 2. SA field is equal to 00001. |
2048 *alu_out = base::bits::RotateRight32(((uint32_t)rt_u, rs_u); | 2048 *alu_out = base::bits::RotateRight32((uint32_t)rt_u, rs_u); |
2049 } | 2049 } |
2050 break; | 2050 break; |
2051 case DSRLV: | 2051 case DSRLV: |
2052 if (sa == 0) { | 2052 if (sa == 0) { |
2053 // Regular logical right-shift of a word by a variable number of | 2053 // Regular logical right-shift of a word by a variable number of |
2054 // bits instruction. SA field is always equal to 0. | 2054 // bits instruction. SA field is always equal to 0. |
2055 *alu_out = rt_u >> rs; | 2055 *alu_out = rt_u >> rs; |
2056 } else { | 2056 } else { |
2057 // Logical right-rotate of a word by a variable number of bits. | 2057 // Logical right-rotate of a word by a variable number of bits. |
2058 // This is special case od SRLV instruction, added in MIPS32 | 2058 // This is special case od SRLV instruction, added in MIPS32 |
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3447 } | 3447 } |
3448 | 3448 |
3449 | 3449 |
3450 #undef UNSUPPORTED | 3450 #undef UNSUPPORTED |
3451 | 3451 |
3452 } } // namespace v8::internal | 3452 } } // namespace v8::internal |
3453 | 3453 |
3454 #endif // USE_SIMULATOR | 3454 #endif // USE_SIMULATOR |
3455 | 3455 |
3456 #endif // V8_TARGET_ARCH_MIPS64 | 3456 #endif // V8_TARGET_ARCH_MIPS64 |
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