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Unified Diff: tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

Issue 914263005: Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge) (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: backup... 9 to go Created 5 years, 10 months ago
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Index: tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
diff --git a/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll b/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
index c16f7c0429d918694553d08895b1e73f4310b96a..d109a854e5668121d94b0b05a2f82a2b0c7f4787 100644
--- a/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
+++ b/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
@@ -1,17 +1,11 @@
; This tests each of the supported NaCl atomic instructions for every
; size allowed.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck --check-prefix=CHECKO2 %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck %s
declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
@@ -53,8 +47,8 @@ entry:
ret i32 %r
}
; CHECK-LABEL: test_atomic_load_8
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, byte
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},byte
define i32 @test_atomic_load_16(i32 %iptr) {
entry:
@@ -64,8 +58,8 @@ entry:
ret i32 %r
}
; CHECK-LABEL: test_atomic_load_16
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, word
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},word
define i32 @test_atomic_load_32(i32 %iptr) {
entry:
@@ -74,8 +68,8 @@ entry:
ret i32 %r
}
; CHECK-LABEL: test_atomic_load_32
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, dword
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},DWORD
define i64 @test_atomic_load_64(i32 %iptr) {
entry:
@@ -84,8 +78,8 @@ entry:
ret i64 %r
}
; CHECK-LABEL: test_atomic_load_64
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
define i32 @test_atomic_load_32_with_arith(i32 %iptr) {
entry:
@@ -98,13 +92,13 @@ next:
ret i32 %r2
}
; CHECK-LABEL: test_atomic_load_32_with_arith
-; CHECK: mov {{.*}}, dword
+; CHECK: mov {{.*}},DWORD
; The next instruction may be a separate load or folded into an add.
;
; In O2 mode, we know that the load and add are going to be fused.
; CHECKO2-LABEL: test_atomic_load_32_with_arith
-; CHECKO2: mov {{.*}}, dword
-; CHECKO2: add {{.*}}, dword
+; CHECKO2: mov {{.*}}, DWORD
+; CHECKO2: add {{.*}}, DWORD
define i32 @test_atomic_load_32_ignored(i32 %iptr) {
entry:
@@ -113,11 +107,11 @@ entry:
ret i32 0
}
; CHECK-LABEL: test_atomic_load_32_ignored
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, dword
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},DWORD
; CHECKO2-LABEL: test_atomic_load_32_ignored
-; CHECKO2: mov {{.*}}, dword
-; CHECKO2: mov {{.*}}, dword
+; CHECKO2: mov {{.*}}, DWORD
+; CHECKO2: mov {{.*}}, DWORD
define i64 @test_atomic_load_64_ignored(i32 %iptr) {
entry:
@@ -126,8 +120,8 @@ entry:
ret i64 0
}
; CHECK-LABEL: test_atomic_load_64_ignored
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
;;; Store
@@ -160,7 +154,7 @@ entry:
ret void
}
; CHECK-LABEL: test_atomic_store_32
-; CHECK: mov dword
+; CHECK: mov DWORD
; CHECK: mfence
define void @test_atomic_store_64(i32 %iptr, i64 %v) {
@@ -170,8 +164,8 @@ entry:
ret void
}
; CHECK-LABEL: test_atomic_store_64
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
; CHECK: mfence
define void @test_atomic_store_64_const(i32 %iptr) {
@@ -181,10 +175,10 @@ entry:
ret void
}
; CHECK-LABEL: test_atomic_store_64_const
-; CHECK: mov {{.*}}, 1942892530
-; CHECK: mov {{.*}}, 2874
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: mov {{.*}},0x73ce2ff2
+; CHECK: mov {{.*}},0xb3a
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
; CHECK: mfence
@@ -203,8 +197,8 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_add_8
; CHECK: lock
-; CHECK-NEXT: xadd byte {{.*}}, [[REG:.*]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK-NEXT: xadd byte {{.*}},[[REG:.*]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
define i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
entry:
@@ -216,8 +210,8 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_add_16
; CHECK: lock
-; CHECK-NEXT: xadd word {{.*}}, [[REG:.*]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK-NEXT: xadd word {{.*}},[[REG:.*]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
define i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
entry:
@@ -227,8 +221,8 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_add_32
; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG:.*]]
-; CHECK: mov {{.*}}, [[REG]]
+; CHECK-NEXT: xadd DWORD {{.*}},[[REG:.*]]
+; CHECK: mov {{.*}},[[REG]]
define i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
entry:
@@ -238,20 +232,20 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_add_64
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: mov ebx,eax
; RHS of add cannot be any of the e[abcd]x regs because they are
; clobbered in the loop, and the RHS needs to be remain live.
-; CHECK: add ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
+; CHECK: add ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
; CHECK: adc ecx, {{.*e.[^x]}}
; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
; It can be esi, edi, or ebp though, for example (so we need to be careful
; about rejecting eb* and ed*.)
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{.[^x]}}]
+; CHECK: jne-{{[0-9]}}
; Test with some more register pressure. When we have an alloca, ebp is
; used to manage the stack frame, so it cannot be used as a register either.
@@ -285,8 +279,8 @@ entry:
; the later use_ptr function call.
; That pretty much leaves esi, or edi as the only viable registers.
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{[ds]}}i]
-; CHECK: call use_ptr
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{[ds]}}i]
+; CHECK: call {{.*}} R_{{.*}} use_ptr
define i32 @test_atomic_rmw_add_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -298,7 +292,7 @@ entry:
; tells us that the destination variable is dead.
; CHECK-LABEL: test_atomic_rmw_add_32_ignored
; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG:.*]]
+; CHECK-NEXT: xadd DWORD {{.*}},[[REG:.*]]
; Atomic RMW 64 needs to be expanded into its own loop.
; Make sure that works w/ non-trivial function bodies.
@@ -322,15 +316,15 @@ err:
}
; CHECK-LABEL: test_atomic_rmw_add_64_loop
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: add ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: mov ebx,eax
+; CHECK: add ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
; CHECK: adc ecx, {{.*e.[^x]}}
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{.[^x]}}]
+; CHECK: jne-{{[0-9]}}
;; sub
@@ -345,8 +339,8 @@ entry:
; CHECK-LABEL: test_atomic_rmw_sub_8
; CHECK: neg [[REG:.*]]
; CHECK: lock
-; CHECK-NEXT: xadd byte {{.*}}, [[REG]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK-NEXT: xadd byte {{.*}},[[REG]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
define i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
entry:
@@ -359,8 +353,8 @@ entry:
; CHECK-LABEL: test_atomic_rmw_sub_16
; CHECK: neg [[REG:.*]]
; CHECK: lock
-; CHECK-NEXT: xadd word {{.*}}, [[REG]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK-NEXT: xadd word {{.*}},[[REG]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
define i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
entry:
@@ -371,8 +365,8 @@ entry:
; CHECK-LABEL: test_atomic_rmw_sub_32
; CHECK: neg [[REG:.*]]
; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG]]
-; CHECK: mov {{.*}}, [[REG]]
+; CHECK-NEXT: xadd DWORD {{.*}},[[REG]]
+; CHECK: mov {{.*}},[[REG]]
define i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
entry:
@@ -382,15 +376,15 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_sub_64
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: mov ebx,eax
; CHECK: sub ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
+; CHECK: mov ecx,edx
; CHECK: sbb ecx, {{.*e.[^x]}}
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{.[^x]}}]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_sub_32_ignored(i32 %iptr, i32 %v) {
@@ -403,7 +397,7 @@ entry:
; CHECK-LABEL: test_atomic_rmw_sub_32_ignored
; CHECK: neg [[REG:.*]]
; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG]]
+; CHECK-NEXT: xadd DWORD {{.*}},[[REG]]
;; or
@@ -416,13 +410,13 @@ entry:
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_or_8
-; CHECK: mov al, byte ptr
+; CHECK: mov al,BYTE PTR
; Dest cannot be eax here, because eax is used for the old value. Also want
; to make sure that cmpxchg's source is the same register.
; CHECK: or [[REG:[^a].]]
; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg BYTE PTR [e{{[^a].}}], [[REG]]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
entry:
@@ -433,11 +427,11 @@ entry:
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_or_16
-; CHECK: mov ax, word ptr
+; CHECK: mov ax,WORD PTR
; CHECK: or [[REG:[^a].]]
; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg WORD PTR [e{{[^a].}}], [[REG]]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
entry:
@@ -446,11 +440,11 @@ entry:
ret i32 %a
}
; CHECK-LABEL: test_atomic_rmw_or_32
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: or [[REG:e[^a].]]
; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg DWORD PTR [e{{[^a].}}], [[REG]]
+; CHECK: jne-{{[0-9]}}
define i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
entry:
@@ -460,15 +454,15 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_or_64
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: mov ebx,eax
; CHECK: or ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
+; CHECK: mov ecx,edx
; CHECK: or ecx, {{.*e.[^x]}}
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{.[^x]}}]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_or_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -480,11 +474,11 @@ entry:
; Could just "lock or", if we inspect the liveness information first.
; Would also need a way to introduce "lock"'edness to binary
; operators without introducing overhead on the more common binary ops.
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: or [[REG:e[^a].]]
; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg DWORD PTR [e{{[^a].}}], [[REG]]
+; CHECK: jne-{{[0-9]}}
;; and
@@ -497,11 +491,11 @@ entry:
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_and_8
-; CHECK: mov al, byte ptr
+; CHECK: mov al,BYTE PTR
; CHECK: and [[REG:[^a].]]
; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg BYTE PTR [e{{[^a].}}], [[REG]]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
entry:
@@ -512,11 +506,11 @@ entry:
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_and_16
-; CHECK: mov ax, word ptr
+; CHECK: mov ax,WORD PTR
; CHECK: and
; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg WORD PTR [e{{[^a].}}]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
entry:
@@ -525,11 +519,11 @@ entry:
ret i32 %a
}
; CHECK-LABEL: test_atomic_rmw_and_32
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: and
; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne-{{[0-9]}}
define i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
entry:
@@ -539,15 +533,15 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_and_64
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: mov ebx,eax
; CHECK: and ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
+; CHECK: mov ecx,edx
; CHECK: and ecx, {{.*e.[^x]}}
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{.[^x]}}]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_and_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -557,11 +551,11 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_and_32_ignored
; Could just "lock and"
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: and
; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne-{{[0-9]}}
;; xor
@@ -574,11 +568,11 @@ entry:
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_xor_8
-; CHECK: mov al, byte ptr
+; CHECK: mov al,BYTE PTR
; CHECK: xor [[REG:[^a].]]
; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg BYTE PTR [e{{[^a].}}], [[REG]]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
entry:
@@ -589,11 +583,11 @@ entry:
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_xor_16
-; CHECK: mov ax, word ptr
+; CHECK: mov ax,WORD PTR
; CHECK: xor
; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg WORD PTR [e{{[^a].}}]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
@@ -603,11 +597,11 @@ entry:
ret i32 %a
}
; CHECK-LABEL: test_atomic_rmw_xor_32
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: xor
; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne-{{[0-9]}}
define i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
entry:
@@ -617,15 +611,15 @@ entry:
}
; CHECK-LABEL: test_atomic_rmw_xor_64
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: mov ebx,eax
; CHECK: or ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
+; CHECK: mov ecx,edx
; CHECK: or ecx, {{.*e.[^x]}}
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{.[^x]}}]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_xor_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -634,11 +628,11 @@ entry:
ret i32 %v
}
; CHECK-LABEL: test_atomic_rmw_xor_32_ignored
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: xor
; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne-{{[0-9]}}
;; exchange
@@ -651,7 +645,7 @@ entry:
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_xchg_8
-; CHECK: xchg byte ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg BYTE PTR {{.*}}, [[REG:.*]]
define i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
entry:
@@ -662,7 +656,7 @@ entry:
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_xchg_16
-; CHECK: xchg word ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg WORD PTR {{.*}}, [[REG:.*]]
define i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
entry:
@@ -671,7 +665,7 @@ entry:
ret i32 %a
}
; CHECK-LABEL: test_atomic_rmw_xchg_32
-; CHECK: xchg dword ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg DWORD PTR {{.*}}, [[REG:.*]]
define i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
entry:
@@ -686,8 +680,8 @@ entry:
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [{{e.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK-NEXT: cmpxchg8b QWORD PTR [{{e.[^x]}}]
+; CHECK: jne-{{[0-9]}}
define i32 @test_atomic_rmw_xchg_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -698,7 +692,7 @@ entry:
; In this case, ignoring the return value doesn't help. The xchg is
; used to do an atomic store.
; CHECK-LABEL: test_atomic_rmw_xchg_32_ignored
-; CHECK: xchg dword ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg DWORD PTR {{.*}}, [[REG:.*]]
;;;; Cmpxchg
@@ -713,11 +707,11 @@ entry:
ret i32 %old_ext
}
; CHECK-LABEL: test_atomic_cmpxchg_8
-; CHECK: mov eax, {{.*}}
+; CHECK: mov eax,{{.*}}
; Need to check that eax isn't used as the address register or the desired.
; since it is already used as the *expected* register.
; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], {{[^a]}}l
+; CHECK-NEXT: cmpxchg BYTE PTR [e{{[^a].}}], {{[^a]}}l
define i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
entry:
@@ -730,9 +724,9 @@ entry:
ret i32 %old_ext
}
; CHECK-LABEL: test_atomic_cmpxchg_16
-; CHECK: mov eax, {{.*}}
+; CHECK: mov eax,{{.*}}
; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}], {{[^a]}}x
+; CHECK-NEXT: cmpxchg WORD PTR [e{{[^a].}}], {{[^a]}}x
define i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
entry:
@@ -742,9 +736,9 @@ entry:
ret i32 %old
}
; CHECK-LABEL: test_atomic_cmpxchg_32
-; CHECK: mov eax, {{.*}}
+; CHECK: mov eax,{{.*}}
; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; CHECK-NEXT: cmpxchg DWORD PTR [e{{[^a].}}], e{{[^a]}}
define i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
entry:
@@ -760,7 +754,7 @@ entry:
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{.[^x]}}]
; edx and eax are already the return registers, so they don't actually
; need to be reshuffled via movs. The next test stores the result
; somewhere, so in that case they do need to be mov'ed.
@@ -782,9 +776,9 @@ entry:
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK-DAG: mov {{.*}}, edx
-; CHECK-DAG: mov {{.*}}, eax
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{.[^x]}}]
+; CHECK-DAG: mov {{.*}},edx
+; CHECK-DAG: mov {{.*}},eax
; Test with some more register pressure. When we have an alloca, ebp is
; used to manage the stack frame, so it cannot be used as a register either.
@@ -814,8 +808,8 @@ entry:
; the later use_ptr function call.
; That pretty much leaves esi, or edi as the only viable registers.
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{[ds]}}i]
-; CHECK: call use_ptr
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{[ds]}}i]
+; CHECK: call {{.*}} R_{{.*}} use_ptr
define i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected, i32 %desired) {
entry:
@@ -825,9 +819,9 @@ entry:
ret i32 0
}
; CHECK-LABEL: test_atomic_cmpxchg_32_ignored
-; CHECK: mov eax, {{.*}}
+; CHECK: mov eax,{{.*}}
; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
+; CHECK-NEXT: cmpxchg DWORD PTR [e{{[^a].}}]
define i64 @test_atomic_cmpxchg_64_ignored(i32 %iptr, i64 %expected, i64 %desired) {
entry:
@@ -843,7 +837,7 @@ entry:
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK-NEXT: cmpxchg8b QWORD PTR [e{{.[^x]}}]
;;;; Fence and is-lock-free.
@@ -871,7 +865,7 @@ entry:
ret i32 %r
}
; CHECK-LABEL: test_atomic_is_lock_free
-; CHECK: mov {{.*}}, 1
+; CHECK: mov {{.*}},0x1
define i32 @test_not_lock_free(i32 %iptr) {
entry:
@@ -881,7 +875,7 @@ entry:
ret i32 %r
}
; CHECK-LABEL: test_not_lock_free
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
define i32 @test_atomic_is_lock_free_ignored(i32 %iptr) {
entry:
@@ -890,7 +884,7 @@ entry:
ret i32 0
}
; CHECK-LABEL: test_atomic_is_lock_free_ignored
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
; This can get optimized out, because it's side-effect-free.
; CHECKO2-LABEL: test_atomic_is_lock_free_ignored
; CHECKO2-NOT: mov {{.*}}, 1
@@ -915,7 +909,7 @@ not_lock_free:
ret i32 %z
}
; CHECK-LABEL: test_atomic_is_lock_free_can_dce
-; CHECK: mov {{.*}}, 1
+; CHECK: mov {{.*}},0x1
; CHECK: ret
; CHECK: add
; CHECK: ret
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