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Unified Diff: tests_lit/llvm2ice_tests/64bit.pnacl.ll

Issue 914263005: Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge) (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 10 months ago
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Index: tests_lit/llvm2ice_tests/64bit.pnacl.ll
diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index d6d6afcd2a5959fdf92a62c33b75eb72ae242472..de6c1c6e205fa32f3e63810f08ed6bc14003d638 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -2,12 +2,9 @@
; particular the patterns for lowering i64 operations into constituent
; i32 operations on x86-32.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
@@ -31,48 +28,51 @@ entry:
}
; CHECK-LABEL: pass64BitArg
; CHECK: sub esp
-; CHECK: mov dword ptr [esp + 4]
-; CHECK: mov dword ptr [esp]
-; CHECK: mov dword ptr [esp + 8], 123
-; CHECK: mov dword ptr [esp + 16]
-; CHECK: mov dword ptr [esp + 12]
-; CHECK: call ignore64BitArgNoInline
+; CHECK: mov DWORD PTR [esp+4]
+; CHECK: mov DWORD PTR [esp]
+; CHECK: mov DWORD PTR [esp+8],123
+; CHECK: mov DWORD PTR [esp+16]
+; CHECK: mov DWORD PTR [esp+12]
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} ignore64BitArgNoInline
; CHECK: sub esp
-; CHECK: mov dword ptr [esp + 4]
-; CHECK: mov dword ptr [esp]
-; CHECK: mov dword ptr [esp + 8], 123
-; CHECK: mov dword ptr [esp + 16]
-; CHECK: mov dword ptr [esp + 12]
-; CHECK: call ignore64BitArgNoInline
+; CHECK: mov DWORD PTR [esp+4]
+; CHECK: mov DWORD PTR [esp]
+; CHECK: mov DWORD PTR [esp+8],123
+; CHECK: mov DWORD PTR [esp+16]
+; CHECK: mov DWORD PTR [esp+12]
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} ignore64BitArgNoInline
; CHECK: sub esp
-; CHECK: mov dword ptr [esp + 4]
-; CHECK: mov dword ptr [esp]
-; CHECK: mov dword ptr [esp + 8], 123
-; CHECK: mov dword ptr [esp + 16]
-; CHECK: mov dword ptr [esp + 12]
-; CHECK: call ignore64BitArgNoInline
+; CHECK: mov DWORD PTR [esp+4]
+; CHECK: mov DWORD PTR [esp]
+; CHECK: mov DWORD PTR [esp+8],123
+; CHECK: mov DWORD PTR [esp+16]
+; CHECK: mov DWORD PTR [esp+12]
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} ignore64BitArgNoInline
;
; OPTM1-LABEL: pass64BitArg
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp + 4]
-; OPTM1: mov dword ptr [esp]
-; OPTM1: mov dword ptr [esp + 8], 123
-; OPTM1: mov dword ptr [esp + 16]
-; OPTM1: mov dword ptr [esp + 12]
+; OPTM1: mov DWORD PTR [esp + 4]
+; OPTM1: mov DWORD PTR [esp]
+; OPTM1: mov DWORD PTR [esp + 8], 123
+; OPTM1: mov DWORD PTR [esp + 16]
+; OPTM1: mov DWORD PTR [esp + 12]
; OPTM1: call ignore64BitArgNoInline
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp + 4]
-; OPTM1: mov dword ptr [esp]
-; OPTM1: mov dword ptr [esp + 8], 123
-; OPTM1: mov dword ptr [esp + 16]
-; OPTM1: mov dword ptr [esp + 12]
+; OPTM1: mov DWORD PTR [esp + 4]
+; OPTM1: mov DWORD PTR [esp]
+; OPTM1: mov DWORD PTR [esp + 8], 123
+; OPTM1: mov DWORD PTR [esp + 16]
+; OPTM1: mov DWORD PTR [esp + 12]
; OPTM1: call ignore64BitArgNoInline
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp + 4]
-; OPTM1: mov dword ptr [esp]
-; OPTM1: mov dword ptr [esp + 8], 123
-; OPTM1: mov dword ptr [esp + 16]
-; OPTM1: mov dword ptr [esp + 12]
+; OPTM1: mov DWORD PTR [esp + 4]
+; OPTM1: mov DWORD PTR [esp]
+; OPTM1: mov DWORD PTR [esp + 8], 123
+; OPTM1: mov DWORD PTR [esp + 16]
+; OPTM1: mov DWORD PTR [esp + 12]
; OPTM1: call ignore64BitArgNoInline
declare i32 @ignore64BitArgNoInline(i64, i32, i64)
@@ -84,24 +84,25 @@ entry:
}
; CHECK-LABEL: pass64BitConstArg
; CHECK: sub esp
-; CHECK: mov dword ptr [esp + 4]
-; CHECK-NEXT: mov dword ptr [esp]
-; CHECK-NEXT: mov dword ptr [esp + 8], 123
+; CHECK: mov DWORD PTR [esp+4]
+; CHECK-NEXT: mov DWORD PTR [esp]
+; CHECK-NEXT: mov DWORD PTR [esp + 8], 123
; Bundle padding might be added (so not using -NEXT).
-; CHECK: mov dword ptr [esp + 16], 3735928559
-; CHECK-NEXT: mov dword ptr [esp + 12], 305419896
+; CHECK: mov DWORD PTR [esp+16],3735928559
+; CHECK-NEXT: mov DWORD PTR [esp + 12], 305419896
; Bundle padding will push the call down.
; CHECK-NOT: mov
-; CHECK: call ignore64BitArgNoInline
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} ignore64BitArgNoInline
;
; OPTM1-LABEL: pass64BitConstArg
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp + 4]
-; OPTM1-NEXT: mov dword ptr [esp]
-; OPTM1-NEXT: mov dword ptr [esp + 8], 123
+; OPTM1: mov DWORD PTR [esp + 4]
+; OPTM1-NEXT: mov DWORD PTR [esp]
+; OPTM1-NEXT: mov DWORD PTR [esp + 8], 123
; Bundle padding might be added (so not using -NEXT).
-; OPTM1: mov dword ptr [esp + 16], 3735928559
-; OPTM1-NEXT: mov dword ptr [esp + 12], 305419896
+; OPTM1: mov DWORD PTR [esp + 16], 3735928559
+; OPTM1-NEXT: mov DWORD PTR [esp + 12], 305419896
; OPTM1-NOT: mov
; OPTM1: call ignore64BitArgNoInline
@@ -110,20 +111,20 @@ entry:
ret i64 %a
}
; CHECK-LABEL: return64BitArg
-; CHECK: mov {{.*}}, dword ptr [esp + 4]
-; CHECK: mov {{.*}}, dword ptr [esp + 8]
+; CHECK: mov {{.*}},DWORD ptr [esp+4]
+; CHECK: mov {{.*}},DWORD ptr [esp+8]
;
; OPTM1-LABEL: return64BitArg
-; OPTM1: mov {{.*}}, dword ptr [esp + 4]
-; OPTM1: mov {{.*}}, dword ptr [esp + 8]
+; OPTM1: mov {{.*}}, DWORD PTR [esp + 4]
+; OPTM1: mov {{.*}}, DWORD PTR [esp + 8]
define internal i64 @return64BitConst() {
entry:
ret i64 -2401053092306725256
}
; CHECK-LABEL: return64BitConst
-; CHECK: mov eax, 305419896
-; CHECK: mov edx, 3735928559
+; CHECK: mov eax,305419896
+; CHECK: mov edx,3735928559
;
; OPTM1-LABEL: return64BitConst
; OPTM1: mov eax, 305419896
@@ -225,7 +226,8 @@ entry:
ret i64 %div
}
; CHECK-LABEL: div64BitSigned
-; CHECK: call __divdi3
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} __divdi3
; OPTM1-LABEL: div64BitSigned
; OPTM1: call __divdi3
@@ -236,13 +238,14 @@ entry:
ret i64 %div
}
; CHECK-LABEL: div64BitSignedConst
-; CHECK: mov dword ptr [esp + 12], 2874
-; CHECK: mov dword ptr [esp + 8], 1942892530
-; CHECK: call __divdi3
+; CHECK: mov DWORD PTR [esp+12],2874
+; CHECK: mov DWORD PTR [esp+8],1942892530
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} __divdi3
;
; OPTM1-LABEL: div64BitSignedConst
-; OPTM1: mov dword ptr [esp + 12], 2874
-; OPTM1: mov dword ptr [esp + 8], 1942892530
+; OPTM1: mov DWORD PTR [esp + 12], 2874
+; OPTM1: mov DWORD PTR [esp + 8], 1942892530
; OPTM1: call __divdi3
define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
@@ -251,7 +254,8 @@ entry:
ret i64 %div
}
; CHECK-LABEL: div64BitUnsigned
-; CHECK: call __udivdi3
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} __udivdi3
;
; OPTM1-LABEL: div64BitUnsigned
; OPTM1: call __udivdi3
@@ -262,7 +266,8 @@ entry:
ret i64 %rem
}
; CHECK-LABEL: rem64BitSigned
-; CHECK: call __moddi3
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} __moddi3
;
; OPTM1-LABEL: rem64BitSigned
; OPTM1: call __moddi3
@@ -273,7 +278,8 @@ entry:
ret i64 %rem
}
; CHECK-LABEL: rem64BitUnsigned
-; CHECK: call __umoddi3
+; CHECK: call
+; CHECK-NEXT: R_{{.*}} __umoddi3
;
; OPTM1-LABEL: rem64BitUnsigned
; OPTM1: call __umoddi3
@@ -487,10 +493,10 @@ entry:
ret i32 %conv
}
; CHECK-LABEL: trunc64To32Signed
-; CHECK: mov eax, dword ptr [esp + 4]
+; CHECK: mov eax,DWORD ptr [esp+4]
;
; OPTM1-LABEL: trunc64To32Signed
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax, DWORD PTR [esp +
define internal i32 @trunc64To16Signed(i64 %a) {
entry:
@@ -499,11 +505,11 @@ entry:
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To16Signed
-; CHECK: mov eax, dword ptr [esp + 4]
+; CHECK: mov eax,DWORD ptr [esp+4]
; CHECK-NEXT: movsx eax, ax
;
; OPTM1-LABEL: trunc64To16Signed
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax, DWORD PTR [esp +
; OPTM1: movsx eax,
define internal i32 @trunc64To8Signed(i64 %a) {
@@ -513,11 +519,11 @@ entry:
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To8Signed
-; CHECK: mov eax, dword ptr [esp + 4]
+; CHECK: mov eax,DWORD ptr [esp+4]
; CHECK-NEXT: movsx eax, al
;
; OPTM1-LABEL: trunc64To8Signed
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax, DWORD PTR [esp +
; OPTM1: movsx eax,
define internal i32 @trunc64To32SignedConst() {
@@ -526,7 +532,7 @@ entry:
ret i32 %conv
}
; CHECK-LABEL: trunc64To32SignedConst
-; CHECK: mov eax, 1942892530
+; CHECK: mov eax,1942892530
;
; OPTM1-LABEL: trunc64To32SignedConst
; OPTM1: mov eax, 1942892530
@@ -538,8 +544,8 @@ entry:
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To16SignedConst
-; CHECK: mov eax, 1942892530
-; CHECK: movsx eax, ax
+; CHECK: mov eax,1942892530
+; CHECK: movsx eax,ax
;
; OPTM1-LABEL: trunc64To16SignedConst
; OPTM1: mov eax, 1942892530
@@ -551,10 +557,10 @@ entry:
ret i32 %conv
}
; CHECK-LABEL: trunc64To32Unsigned
-; CHECK: mov eax, dword ptr [esp + 4]
+; CHECK: mov eax,DWORD ptr [esp+4]
;
; OPTM1-LABEL: trunc64To32Unsigned
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax, DWORD PTR [esp +
define internal i32 @trunc64To16Unsigned(i64 %a) {
entry:
@@ -563,11 +569,11 @@ entry:
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To16Unsigned
-; CHECK: mov eax, dword ptr [esp + 4]
+; CHECK: mov eax,DWORD ptr [esp+4]
; CHECK-NEXT: movzx eax, ax
;
; OPTM1-LABEL: trunc64To16Unsigned
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax, DWORD PTR [esp +
; OPTM1: movzx eax,
define internal i32 @trunc64To8Unsigned(i64 %a) {
@@ -577,11 +583,11 @@ entry:
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To8Unsigned
-; CHECK: mov eax, dword ptr [esp + 4]
+; CHECK: mov eax,DWORD ptr [esp+4]
; CHECK-NEXT: movzx eax, al
;
; OPTM1-LABEL: trunc64To8Unsigned
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax, DWORD PTR [esp +
; OPTM1: movzx eax,
define internal i32 @trunc64To1(i64 %a) {
@@ -592,12 +598,12 @@ entry:
ret i32 %tobool.ret_ext
}
; CHECK-LABEL: trunc64To1
-; CHECK: mov eax, dword ptr [esp + 4]
+; CHECK: mov eax,DWORD ptr [esp+4]
; CHECK: and eax, 1
; CHECK: and eax, 1
;
; OPTM1-LABEL: trunc64To1
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax, DWORD PTR [esp +
; OPTM1: and eax, 1
; OPTM1: and eax, 1
@@ -665,7 +671,7 @@ entry:
}
; CHECK-LABEL: zext32To64
; CHECK: mov
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0
;
; OPTM1-LABEL: zext32To64
; OPTM1: mov
@@ -679,7 +685,7 @@ entry:
}
; CHECK-LABEL: zext16To64
; CHECK: movzx
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0
;
; OPTM1-LABEL: zext16To64
; OPTM1: movzx
@@ -693,7 +699,7 @@ entry:
}
; CHECK-LABEL: zext8To64
; CHECK: movzx
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0
;
; OPTM1-LABEL: zext8To64
; OPTM1: movzx
@@ -707,7 +713,7 @@ entry:
}
; CHECK-LABEL: zext1To64
; CHECK: and {{.*}}, 1
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0
;
; OPTM1-LABEL: zext1To64
; OPTM1: and {{.*}}, 1
@@ -1142,13 +1148,13 @@ entry:
ret i64 %v0
}
; CHECK-LABEL: load64
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
-; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]]
-; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]] + 4]
+; CHECK: mov e[[REGISTER:[a-z]+]],DWORD ptr [esp+4]
+; CHECK-NEXT: mov {{.*}}, DWORD PTR [e[[REGISTER]]]
+; CHECK-NEXT: mov {{.*}}, DWORD PTR [e[[REGISTER]] + 4]
;
; OPTM1-LABEL: load64
-; OPTM1: mov e{{..}}, dword ptr [e{{..}}]
-; OPTM1: mov e{{..}}, dword ptr [e{{..}} + 4]
+; OPTM1: mov e{{..}}, DWORD PTR [e{{..}}]
+; OPTM1: mov e{{..}}, DWORD PTR [e{{..}} + 4]
define internal void @store64(i32 %a, i64 %value) {
entry:
@@ -1157,13 +1163,13 @@ entry:
ret void
}
; CHECK-LABEL: store64
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
-; CHECK: mov dword ptr [e[[REGISTER]] + 4],
-; CHECK: mov dword ptr [e[[REGISTER]]],
+; CHECK: mov e[[REGISTER:[a-z]+]],DWORD ptr [esp+4]
+; CHECK: mov DWORD PTR [e[[REGISTER]]+4],
+; CHECK: mov DWORD PTR [e[[REGISTER]]],
;
; OPTM1-LABEL: store64
-; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]] + 4],
-; OPTM1: mov dword ptr [e[[REGISTER]]],
+; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]] + 4],
+; OPTM1: mov DWORD PTR [e[[REGISTER]]],
define internal void @store64Const(i32 %a) {
entry:
@@ -1172,13 +1178,13 @@ entry:
ret void
}
; CHECK-LABEL: store64Const
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
-; CHECK: mov dword ptr [e[[REGISTER]] + 4], 3735928559
-; CHECK: mov dword ptr [e[[REGISTER]]], 305419896
+; CHECK: mov e[[REGISTER:[a-z]+]],DWORD ptr [esp+4]
+; CHECK: mov DWORD PTR [e[[REGISTER]]+4],3735928559
+; CHECK: mov DWORD PTR [e[[REGISTER]]],305419896
;
; OPTM1-LABEL: store64Const
-; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]] + 4], 3735928559
-; OPTM1: mov dword ptr [e[[REGISTER]]], 305419896
+; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]] + 4], 3735928559
+; OPTM1: mov DWORD PTR [e[[REGISTER]]], 305419896
define internal i64 @select64VarVar(i64 %a, i64 %b) {
entry:
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