Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge)

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN:   | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN:   | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN:   | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
 ; RUN:   | FileCheck --check-prefix=OPTM1 %s
 
 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
 
 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) {
 entry:
   ret i32 %b
 }
 
 define internal i32 @pass64BitArg(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f) {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 %b)
   %call1 = call i32 @ignore64BitArgNoInline(i64 %c, i32 123, i64 %d)
   %call2 = call i32 @ignore64BitArgNoInline(i64 %e, i32 123, i64 %f)
   %add = add i32 %call1, %call
   %add3 = add i32 %add, %call2
   ret i32 %add3
 }
 ; CHECK-LABEL: pass64BitArg
 ; CHECK:      sub     esp
-; CHECK:      mov     dword ptr [esp + 4]
-; CHECK:      mov     dword ptr [esp]
-; CHECK:      mov     dword ptr [esp + 8], 123
-; CHECK:      mov     dword ptr [esp + 16]
-; CHECK:      mov     dword ptr [esp + 12]
-; CHECK:      call    ignore64BitArgNoInline
+; CHECK:      mov     DWORD PTR [esp+4]
+; CHECK:      mov     DWORD PTR [esp]
+; CHECK:      mov     DWORD PTR [esp+8],123
+; CHECK:      mov     DWORD PTR [esp+16]
+; CHECK:      mov     DWORD PTR [esp+12]
+; CHECK:      call
+; CHECK-NEXT: R_{{.*}}    ignore64BitArgNoInline
 ; CHECK:      sub     esp
-; CHECK:      mov     dword ptr [esp + 4]
-; CHECK:      mov     dword ptr [esp]
-; CHECK:      mov     dword ptr [esp + 8], 123
-; CHECK:      mov     dword ptr [esp + 16]
-; CHECK:      mov     dword ptr [esp + 12]
-; CHECK:      call    ignore64BitArgNoInline
+; CHECK:      mov     DWORD PTR [esp+4]
+; CHECK:      mov     DWORD PTR [esp]
+; CHECK:      mov     DWORD PTR [esp+8],123
+; CHECK:      mov     DWORD PTR [esp+16]
+; CHECK:      mov     DWORD PTR [esp+12]
+; CHECK:      call
+; CHECK-NEXT: R_{{.*}}    ignore64BitArgNoInline
 ; CHECK:      sub     esp
-; CHECK:      mov     dword ptr [esp + 4]
-; CHECK:      mov     dword ptr [esp]
-; CHECK:      mov     dword ptr [esp + 8], 123
-; CHECK:      mov     dword ptr [esp + 16]
-; CHECK:      mov     dword ptr [esp + 12]
-; CHECK:      call    ignore64BitArgNoInline
+; CHECK:      mov     DWORD PTR [esp+4]
+; CHECK:      mov     DWORD PTR [esp]
+; CHECK:      mov     DWORD PTR [esp+8],123
+; CHECK:      mov     DWORD PTR [esp+16]
+; CHECK:      mov     DWORD PTR [esp+12]
+; CHECK:      call
+; CHECK-NEXT: R_{{.*}}    ignore64BitArgNoInline
 ;
 ; OPTM1-LABEL: pass64BitArg
 ; OPTM1:      sub     esp
-; OPTM1:      mov     dword ptr [esp + 4]
-; OPTM1:      mov     dword ptr [esp]
-; OPTM1:      mov     dword ptr [esp + 8], 123
-; OPTM1:      mov     dword ptr [esp + 16]
-; OPTM1:      mov     dword ptr [esp + 12]
+; OPTM1:      mov     DWORD PTR [esp + 4]
+; OPTM1:      mov     DWORD PTR [esp]
+; OPTM1:      mov     DWORD PTR [esp + 8], 123
+; OPTM1:      mov     DWORD PTR [esp + 16]
+; OPTM1:      mov     DWORD PTR [esp + 12]
 ; OPTM1:      call    ignore64BitArgNoInline
 ; OPTM1:      sub     esp
-; OPTM1:      mov     dword ptr [esp + 4]
-; OPTM1:      mov     dword ptr [esp]
-; OPTM1:      mov     dword ptr [esp + 8], 123
-; OPTM1:      mov     dword ptr [esp + 16]
-; OPTM1:      mov     dword ptr [esp + 12]
+; OPTM1:      mov     DWORD PTR [esp + 4]
+; OPTM1:      mov     DWORD PTR [esp]
+; OPTM1:      mov     DWORD PTR [esp + 8], 123
+; OPTM1:      mov     DWORD PTR [esp + 16]
+; OPTM1:      mov     DWORD PTR [esp + 12]
 ; OPTM1:      call    ignore64BitArgNoInline
 ; OPTM1:      sub     esp
-; OPTM1:      mov     dword ptr [esp + 4]
-; OPTM1:      mov     dword ptr [esp]
-; OPTM1:      mov     dword ptr [esp + 8], 123
-; OPTM1:      mov     dword ptr [esp + 16]
-; OPTM1:      mov     dword ptr [esp + 12]
+; OPTM1:      mov     DWORD PTR [esp + 4]
+; OPTM1:      mov     DWORD PTR [esp]
+; OPTM1:      mov     DWORD PTR [esp + 8], 123
+; OPTM1:      mov     DWORD PTR [esp + 16]
+; OPTM1:      mov     DWORD PTR [esp + 12]
 ; OPTM1:      call    ignore64BitArgNoInline
 
 declare i32 @ignore64BitArgNoInline(i64, i32, i64)
 
 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 -2401053092306725256)
   ret i32 %call
 }
 ; CHECK-LABEL: pass64BitConstArg
 ; CHECK:      sub     esp
-; CHECK:      mov     dword ptr [esp + 4]
-; CHECK-NEXT: mov     dword ptr [esp]
-; CHECK-NEXT: mov     dword ptr [esp + 8], 123
+; CHECK:      mov     DWORD PTR [esp+4]
+; CHECK-NEXT: mov     DWORD PTR [esp]
+; CHECK-NEXT: mov     DWORD PTR [esp + 8], 123
 ; Bundle padding might be added (so not using -NEXT).
-; CHECK:      mov     dword ptr [esp + 16], 3735928559
-; CHECK-NEXT: mov     dword ptr [esp + 12], 305419896
+; CHECK:      mov     DWORD PTR [esp+16],3735928559
+; CHECK-NEXT: mov     DWORD PTR [esp + 12], 305419896
 ; Bundle padding will push the call down.
 ; CHECK-NOT:  mov
-; CHECK:      call    ignore64BitArgNoInline
+; CHECK:      call
+; CHECK-NEXT: R_{{.*}}    ignore64BitArgNoInline
 ;
 ; OPTM1-LABEL: pass64BitConstArg
 ; OPTM1:      sub     esp
-; OPTM1:      mov     dword ptr [esp + 4]
-; OPTM1-NEXT: mov     dword ptr [esp]
-; OPTM1-NEXT: mov     dword ptr [esp + 8], 123
+; OPTM1:      mov     DWORD PTR [esp + 4]
+; OPTM1-NEXT: mov     DWORD PTR [esp]
+; OPTM1-NEXT: mov     DWORD PTR [esp + 8], 123
 ; Bundle padding might be added (so not using -NEXT).
-; OPTM1:      mov     dword ptr [esp + 16], 3735928559
-; OPTM1-NEXT: mov     dword ptr [esp + 12], 305419896
+; OPTM1:      mov     DWORD PTR [esp + 16], 3735928559
+; OPTM1-NEXT: mov     DWORD PTR [esp + 12], 305419896
 ; OPTM1-NOT:  mov
 ; OPTM1:      call    ignore64BitArgNoInline
 
 define internal i64 @return64BitArg(i64 %a) {
 entry:
   ret i64 %a
 }
 ; CHECK-LABEL: return64BitArg
-; CHECK: mov     {{.*}}, dword ptr [esp + 4]
-; CHECK: mov     {{.*}}, dword ptr [esp + 8]
+; CHECK: mov     {{.*}},DWORD ptr [esp+4]
+; CHECK: mov     {{.*}},DWORD ptr [esp+8]
 ;
 ; OPTM1-LABEL: return64BitArg
-; OPTM1: mov     {{.*}}, dword ptr [esp + 4]
-; OPTM1: mov     {{.*}}, dword ptr [esp + 8]
+; OPTM1: mov     {{.*}}, DWORD PTR [esp + 4]
+; OPTM1: mov     {{.*}}, DWORD PTR [esp + 8]
 
 define internal i64 @return64BitConst() {
 entry:
   ret i64 -2401053092306725256
 }
 ; CHECK-LABEL: return64BitConst
-; CHECK: mov     eax, 305419896
-; CHECK: mov     edx, 3735928559
+; CHECK: mov     eax,305419896
+; CHECK: mov     edx,3735928559
 ;
 ; OPTM1-LABEL: return64BitConst
 ; OPTM1: mov     eax, 305419896
 ; OPTM1: mov     edx, 3735928559
 
 define internal i64 @add64BitSigned(i64 %a, i64 %b) {
 entry:
   %add = add i64 %b, %a
   ret i64 %add
 }
@@ skipping 81 matching lines @@
 ; OPTM1: mul
 ; OPTM1: add
 ; OPTM1: add
 
 define internal i64 @div64BitSigned(i64 %a, i64 %b) {
 entry:
   %div = sdiv i64 %a, %b
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitSigned
-; CHECK: call    __divdi3
+; CHECK: call
+; CHECK-NEXT: R_{{.*}}    __divdi3
 
 ; OPTM1-LABEL: div64BitSigned
 ; OPTM1: call    __divdi3
 
 define internal i64 @div64BitSignedConst(i64 %a) {
 entry:
   %div = sdiv i64 %a, 12345678901234
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitSignedConst
-; CHECK: mov     dword ptr [esp + 12], 2874
-; CHECK: mov     dword ptr [esp + 8],  1942892530
-; CHECK: call    __divdi3
+; CHECK: mov     DWORD PTR [esp+12],2874
+; CHECK: mov     DWORD PTR [esp+8],1942892530
+; CHECK: call
+; CHECK-NEXT: R_{{.*}}    __divdi3
 ;
 ; OPTM1-LABEL: div64BitSignedConst
-; OPTM1: mov     dword ptr [esp + 12], 2874
-; OPTM1: mov     dword ptr [esp + 8],  1942892530
+; OPTM1: mov     DWORD PTR [esp + 12], 2874
+; OPTM1: mov     DWORD PTR [esp + 8],  1942892530
 ; OPTM1: call    __divdi3
 
 define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %div = udiv i64 %a, %b
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitUnsigned
-; CHECK: call    __udivdi3
+; CHECK: call
+; CHECK-NEXT: R_{{.*}}    __udivdi3
 ;
 ; OPTM1-LABEL: div64BitUnsigned
 ; OPTM1: call    __udivdi3
 
 define internal i64 @rem64BitSigned(i64 %a, i64 %b) {
 entry:
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
 ; CHECK-LABEL: rem64BitSigned
-; CHECK: call    __moddi3
+; CHECK: call
+; CHECK-NEXT: R_{{.*}}    __moddi3
 ;
 ; OPTM1-LABEL: rem64BitSigned
 ; OPTM1: call    __moddi3
 
 define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
 ; CHECK-LABEL: rem64BitUnsigned
-; CHECK: call    __umoddi3
+; CHECK: call
+; CHECK-NEXT: R_{{.*}}    __umoddi3
 ;
 ; OPTM1-LABEL: rem64BitUnsigned
 ; OPTM1: call    __umoddi3
 
 define internal i64 @shl64BitSigned(i64 %a, i64 %b) {
 entry:
   %shl = shl i64 %a, %b
   ret i64 %shl
 }
 ; CHECK-LABEL: shl64BitSigned
@@ skipping 193 matching lines @@
 ; OPTM1-LABEL: xor64BitUnsigned
 ; OPTM1: xor
 ; OPTM1: xor
 
 define internal i32 @trunc64To32Signed(i64 %a) {
 entry:
   %conv = trunc i64 %a to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32Signed
-; CHECK: mov     eax, dword ptr [esp + 4]
+; CHECK: mov     eax,DWORD ptr [esp+4]
 ;
 ; OPTM1-LABEL: trunc64To32Signed
-; OPTM1: mov     eax, dword ptr [esp +
+; OPTM1: mov     eax, DWORD PTR [esp +
 
 define internal i32 @trunc64To16Signed(i64 %a) {
 entry:
   %conv = trunc i64 %a to i16
   %conv.ret_ext = sext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To16Signed
-; CHECK:      mov     eax, dword ptr [esp + 4]
+; CHECK:      mov     eax,DWORD ptr [esp+4]
 ; CHECK-NEXT: movsx  eax, ax
 ;
 ; OPTM1-LABEL: trunc64To16Signed
-; OPTM1:      mov     eax, dword ptr [esp +
+; OPTM1:      mov     eax, DWORD PTR [esp +
 ; OPTM1: movsx  eax,
 
 define internal i32 @trunc64To8Signed(i64 %a) {
 entry:
   %conv = trunc i64 %a to i8
   %conv.ret_ext = sext i8 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To8Signed
-; CHECK:      mov     eax, dword ptr [esp + 4]
+; CHECK:      mov     eax,DWORD ptr [esp+4]
 ; CHECK-NEXT: movsx  eax, al
 ;
 ; OPTM1-LABEL: trunc64To8Signed
-; OPTM1:      mov     eax, dword ptr [esp +
+; OPTM1:      mov     eax, DWORD PTR [esp +
 ; OPTM1: movsx  eax,
 
 define internal i32 @trunc64To32SignedConst() {
 entry:
   %conv = trunc i64 12345678901234 to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32SignedConst
-; CHECK: mov eax, 1942892530
+; CHECK: mov eax,1942892530
 ;
 ; OPTM1-LABEL: trunc64To32SignedConst
 ; OPTM1: mov eax, 1942892530
 
 define internal i32 @trunc64To16SignedConst() {
 entry:
   %conv = trunc i64 12345678901234 to i16
   %conv.ret_ext = sext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To16SignedConst
-; CHECK: mov eax, 1942892530
-; CHECK: movsx eax, ax
+; CHECK: mov eax,1942892530
+; CHECK: movsx eax,ax
 ;
 ; OPTM1-LABEL: trunc64To16SignedConst
 ; OPTM1: mov eax, 1942892530
 ; OPTM1: movsx eax,
 
 define internal i32 @trunc64To32Unsigned(i64 %a) {
 entry:
   %conv = trunc i64 %a to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32Unsigned
-; CHECK: mov     eax, dword ptr [esp + 4]
+; CHECK: mov     eax,DWORD ptr [esp+4]
 ;
 ; OPTM1-LABEL: trunc64To32Unsigned
-; OPTM1: mov     eax, dword ptr [esp +
+; OPTM1: mov     eax, DWORD PTR [esp +
 
 define internal i32 @trunc64To16Unsigned(i64 %a) {
 entry:
   %conv = trunc i64 %a to i16
   %conv.ret_ext = zext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To16Unsigned
-; CHECK:      mov     eax, dword ptr [esp + 4]
+; CHECK:      mov     eax,DWORD ptr [esp+4]
 ; CHECK-NEXT: movzx  eax, ax
 ;
 ; OPTM1-LABEL: trunc64To16Unsigned
-; OPTM1:      mov     eax, dword ptr [esp +
+; OPTM1:      mov     eax, DWORD PTR [esp +
 ; OPTM1: movzx  eax,
 
 define internal i32 @trunc64To8Unsigned(i64 %a) {
 entry:
   %conv = trunc i64 %a to i8
   %conv.ret_ext = zext i8 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To8Unsigned
-; CHECK:      mov     eax, dword ptr [esp + 4]
+; CHECK:      mov     eax,DWORD ptr [esp+4]
 ; CHECK-NEXT: movzx  eax, al
 ;
 ; OPTM1-LABEL: trunc64To8Unsigned
-; OPTM1: mov    eax, dword ptr [esp +
+; OPTM1: mov    eax, DWORD PTR [esp +
 ; OPTM1: movzx  eax,
 
 define internal i32 @trunc64To1(i64 %a) {
 entry:
 ;  %tobool = icmp ne i64 %a, 0
   %tobool = trunc i64 %a to i1
   %tobool.ret_ext = zext i1 %tobool to i32
   ret i32 %tobool.ret_ext
 }
 ; CHECK-LABEL: trunc64To1
-; CHECK:      mov     eax, dword ptr [esp + 4]
+; CHECK:      mov     eax,DWORD ptr [esp+4]
 ; CHECK:      and     eax, 1
 ; CHECK:      and     eax, 1
 ;
 ; OPTM1-LABEL: trunc64To1
-; OPTM1:      mov     eax, dword ptr [esp +
+; OPTM1:      mov     eax, DWORD PTR [esp +
 ; OPTM1:      and     eax, 1
 ; OPTM1:      and     eax, 1
 
 define internal i64 @sext32To64(i32 %a) {
 entry:
   %conv = sext i32 %a to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext32To64
 ; CHECK: mov
@@ skipping 47 matching lines @@
 ; OPTM1: shl {{.*}}, 31
 ; OPTM1: sar {{.*}}, 31
 
 define internal i64 @zext32To64(i32 %a) {
 entry:
   %conv = zext i32 %a to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext32To64
 ; CHECK: mov
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0
 ;
 ; OPTM1-LABEL: zext32To64
 ; OPTM1: mov
 ; OPTM1: mov {{.*}}, 0
 
 define internal i64 @zext16To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i16
   %conv = zext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext16To64
 ; CHECK: movzx
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0
 ;
 ; OPTM1-LABEL: zext16To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}}, 0
 
 define internal i64 @zext8To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i8
   %conv = zext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext8To64
 ; CHECK: movzx
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0
 ;
 ; OPTM1-LABEL: zext8To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}}, 0
 
 define internal i64 @zext1To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i1
   %conv = zext i1 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext1To64
 ; CHECK: and {{.*}}, 1
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0
 ;
 ; OPTM1-LABEL: zext1To64
 ; OPTM1: and {{.*}}, 1
 ; OPTM1: mov {{.*}}, 0
 
 define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp eq i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
@@ skipping 414 matching lines @@
 ; OPTM1: cmp
 ; OPTM1: jbe
 
 define internal i64 @load64(i32 %a) {
 entry:
   %__1 = inttoptr i32 %a to i64*
   %v0 = load i64* %__1, align 1
   ret i64 %v0
 }
 ; CHECK-LABEL: load64
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
-; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]]
-; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]] + 4]
+; CHECK: mov e[[REGISTER:[a-z]+]],DWORD ptr [esp+4]
+; CHECK-NEXT: mov {{.*}}, DWORD PTR [e[[REGISTER]]]
+; CHECK-NEXT: mov {{.*}}, DWORD PTR [e[[REGISTER]] + 4]
 ;
 ; OPTM1-LABEL: load64
-; OPTM1: mov e{{..}}, dword ptr [e{{..}}]
-; OPTM1: mov e{{..}}, dword ptr [e{{..}} + 4]
+; OPTM1: mov e{{..}}, DWORD PTR [e{{..}}]
+; OPTM1: mov e{{..}}, DWORD PTR [e{{..}} + 4]
 
 define internal void @store64(i32 %a, i64 %value) {
 entry:
   %__2 = inttoptr i32 %a to i64*
   store i64 %value, i64* %__2, align 1
   ret void
 }
 ; CHECK-LABEL: store64
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
-; CHECK: mov dword ptr [e[[REGISTER]] + 4],
-; CHECK: mov dword ptr [e[[REGISTER]]],
+; CHECK: mov e[[REGISTER:[a-z]+]],DWORD ptr [esp+4]
+; CHECK: mov DWORD PTR [e[[REGISTER]]+4],
+; CHECK: mov DWORD PTR [e[[REGISTER]]],
 ;
 ; OPTM1-LABEL: store64
-; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]] + 4],
-; OPTM1: mov dword ptr [e[[REGISTER]]],
+; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]] + 4],
+; OPTM1: mov DWORD PTR [e[[REGISTER]]],
 
 define internal void @store64Const(i32 %a) {
 entry:
   %__1 = inttoptr i32 %a to i64*
   store i64 -2401053092306725256, i64* %__1, align 1
   ret void
 }
 ; CHECK-LABEL: store64Const
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
-; CHECK: mov dword ptr [e[[REGISTER]] + 4], 3735928559
-; CHECK: mov dword ptr [e[[REGISTER]]], 305419896
+; CHECK: mov e[[REGISTER:[a-z]+]],DWORD ptr [esp+4]
+; CHECK: mov DWORD PTR [e[[REGISTER]]+4],3735928559
+; CHECK: mov DWORD PTR [e[[REGISTER]]],305419896
 ;
 ; OPTM1-LABEL: store64Const
-; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]] + 4], 3735928559
-; OPTM1: mov dword ptr [e[[REGISTER]]], 305419896
+; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]] + 4], 3735928559
+; OPTM1: mov DWORD PTR [e[[REGISTER]]], 305419896
 
 define internal i64 @select64VarVar(i64 %a, i64 %b) {
 entry:
   %cmp = icmp ult i64 %a, %b
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 }
 ; CHECK-LABEL: select64VarVar
 ; CHECK: cmp
 ; CHECK: jb
@@ skipping 106 matching lines @@
 
 if.end3:                                          ; preds = %if.then2, %if.end
   ret void
 }
 ; The following checks are not strictly necessary since one of the RUN
 ; lines actually runs the output through the assembler.
 ; CHECK-LABEL: icmpLt64Imm
 ; CHECK-NOT: cmp {{[0-9]+}},
 ; OPTM1-LABEL: icmpLt64Imm
 ; OPTM1-NOT: cmp {{[0-9]+}},