VM: Align implementations of assembler constant pools.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 1569 matching lines @@
   if (object.IsSmi()) {
     LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()), cond);
   } else if (object.InVMHeap() || !allow_constant_pool()) {
     // Make sure that class CallPattern is able to decode this load immediate.
     const int32_t object_raw = reinterpret_cast<int32_t>(object.raw());
     LoadImmediate(rd, object_raw, cond);
   } else {
     // Make sure that class CallPattern is able to decode this load from the
     // object pool.
     const int32_t offset =
-        Array::data_offset() + 4*AddObject(object) - kHeapObjectTag;
-    LoadWordFromPoolOffset(rd, offset, cond);
+        Array::element_offset(object_pool_.FindObject(object, kNotPatchable));
+    LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, cond);
   }
 }
 
 
 void Assembler::PushObject(const Object& object) {
   LoadObject(IP, object);
   Push(IP);
 }
 
 
@@ skipping 1064 matching lines @@
   blx(LR);  // Use blx instruction so that the return branch prediction works.
 }
 
 
 void Assembler::BranchLinkPatchable(const ExternalLabel* label) {
   // Make sure that class CallPattern is able to patch the label referred
   // to by this code sequence.
   // For added code robustness, use 'blx lr' in a patchable sequence and
   // use 'blx ip' in a non-patchable sequence (see other BranchLink flavors).
   const int32_t offset =
-      Array::data_offset() + 4*AddExternalLabel(label) - kHeapObjectTag;
-  LoadWordFromPoolOffset(LR, offset);
+      Array::element_offset(object_pool_.FindExternalLabel(label, kPatchable));
+  LoadWordFromPoolOffset(LR, offset - kHeapObjectTag);
   blx(LR);  // Use blx instruction so that the return branch prediction works.
 }
 
 
 void Assembler::BranchLinkOffset(Register base, int32_t offset) {
   ASSERT(base != PC);
   ASSERT(base != IP);
   LoadFromOffset(kWord, IP, base, offset);
   blx(IP);  // Use blx instruction so that the return branch prediction works.
 }
@@ skipping 15 matching lines @@
   } else {
     ASSERT(version == ARMv7);
     const uint16_t value_low = Utils::Low16Bits(value);
     const uint16_t value_high = Utils::High16Bits(value);
     movw(rd, value_low, cond);
     movt(rd, value_high, cond);
   }
 }
 
 
-void Assembler::LoadDecodableImmediate(
-    Register rd, int32_t value, Condition cond) {
-  const ARMVersion version = TargetCPUFeatures::arm_version();
-  if ((version == ARMv5TE) || (version == ARMv6)) {
-    LoadPatchableImmediate(rd, value, cond);
-  } else {
-    ASSERT(version == ARMv7);
-    movw(rd, Utils::Low16Bits(value), cond);
-    const uint16_t value_high = Utils::High16Bits(value);
-    if (value_high != 0) {
-      movt(rd, value_high, cond);
-    }
-  }
-}
-
-
 void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
   Operand o;
   if (Operand::CanHold(value, &o)) {
     mov(rd, o, cond);
   } else if (Operand::CanHold(~value, &o)) {
     mvn(rd, o, cond);
   } else {
-    LoadDecodableImmediate(rd, value, cond);
+    LoadPatchableImmediate(rd, value, cond);

[zra, 2015/02/09 15:30:30]

What is the reason for this change? Does this immediate load now need to be
patchable? If so, then the first two cases should also be removed. If not, then
LoadDecodableImmediate gives a shorter sequence for < 16 bit values.

[Florian Schneider, 2015/02/09 15:49:41]

No, I missed the case for <16 bit values. I'll undo this part.

   }
 }
 
 
 void Assembler::LoadSImmediate(SRegister sd, float value, Condition cond) {
   if (!vmovs(sd, value, cond)) {
     const DRegister dd = static_cast<DRegister>(sd >> 1);
     const int index = sd & 1;
     LoadImmediate(IP, bit_cast<int32_t, float>(value), cond);
     vmovdr(dd, index, IP, cond);
@@ skipping 265 matching lines @@
     sub(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
     if (Operand::CanHold(~value, &o)) {
       mvn(IP, o, cond);
       add(rd, rn, Operand(IP), cond);
     } else if (Operand::CanHold(~(-value), &o)) {
       mvn(IP, o, cond);
       sub(rd, rn, Operand(IP), cond);
     } else {
-      LoadDecodableImmediate(IP, value, cond);
+      LoadPatchableImmediate(IP, value, cond);
       add(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value,
                                      Condition cond) {
   Operand o;
   if (Operand::CanHold(value, &o)) {
     // Handles value == kMinInt32.
     adds(rd, rn, o, cond);
   } else if (Operand::CanHold(-value, &o)) {
     ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
     subs(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
     if (Operand::CanHold(~value, &o)) {
       mvn(IP, o, cond);
       adds(rd, rn, Operand(IP), cond);
     } else if (Operand::CanHold(~(-value), &o)) {
       ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
       mvn(IP, o, cond);
       subs(rd, rn, Operand(IP), cond);
     } else {
-      LoadDecodableImmediate(IP, value, cond);
+      LoadPatchableImmediate(IP, value, cond);
       adds(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
 void Assembler::SubImmediateSetFlags(Register rd, Register rn, int32_t value,
                                     Condition cond) {
   Operand o;
   if (Operand::CanHold(value, &o)) {
     // Handles value == kMinInt32.
     subs(rd, rn, o, cond);
   } else if (Operand::CanHold(-value, &o)) {
     ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
     adds(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
     if (Operand::CanHold(~value, &o)) {
       mvn(IP, o, cond);
       subs(rd, rn, Operand(IP), cond);
     } else if (Operand::CanHold(~(-value), &o)) {
       ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
       mvn(IP, o, cond);
       adds(rd, rn, Operand(IP), cond);
     } else {
-      LoadDecodableImmediate(IP, value, cond);
+      LoadPatchableImmediate(IP, value, cond);
       subs(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AndImmediate(Register rd, Register rs, int32_t imm,
                              Condition cond) {
   Operand o;
   if (Operand::CanHold(imm, &o)) {
@@ skipping 451 matching lines @@
   // 'unstop' and continue execution in the simulator or jump to the next
   // instruction in gdb.
   Label stop;
   b(&stop);
   Emit(reinterpret_cast<int32_t>(message));
   Bind(&stop);
   svc(kStopMessageSvcCode);
 }
 
 
-int32_t Assembler::AddObject(const Object& obj) {
-  ASSERT(obj.IsNotTemporaryScopedHandle());
-  ASSERT(obj.IsOld());
-  if (object_pool_.IsNull()) {
-    // The object pool cannot be used in the vm isolate.
-    ASSERT(Isolate::Current() != Dart::vm_isolate());
-    object_pool_ = GrowableObjectArray::New(Heap::kOld);
-  }
-
-  intptr_t index = object_pool_index_table_.Lookup(&obj);
-  if (index != ObjIndexPair::kNoIndex) {
-    return index;
-  }
-
-  object_pool_.Add(obj, Heap::kOld);
-  object_pool_index_table_.Insert(
-      ObjIndexPair(&obj, object_pool_.Length() - 1));
-  return object_pool_.Length() - 1;
-}
-
-
-int32_t Assembler::AddExternalLabel(const ExternalLabel* label) {
-  if (object_pool_.IsNull()) {
-    // The object pool cannot be used in the vm isolate.
-    ASSERT(Isolate::Current() != Dart::vm_isolate());
-    object_pool_ = GrowableObjectArray::New(Heap::kOld);
-  }
-  const word address = label->address();
-  ASSERT(Utils::IsAligned(address, 4));
-  // The address is stored in the object array as a RawSmi.
-  const Smi& smi = Smi::Handle(Smi::New(address >> kSmiTagShift));
-  // Do not reuse an existing entry, since each reference may be patched
-  // independently.
-  object_pool_.Add(smi, Heap::kOld);
-  return object_pool_.Length() - 1;
-}
-
-
 Address Assembler::ElementAddressForIntIndex(bool is_load,
                                              bool is_external,
                                              intptr_t cid,
                                              intptr_t index_scale,
                                              Register array,
                                              intptr_t index,
                                              Register temp) {
   const int64_t offset_base =
       (is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
   const int64_t offset = offset_base +
@@ skipping 75 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM