Improve generated MIPS code for conditional expressions and branches by delaying

runtime/vm/flow_graph_compiler_mips.cc

Index: runtime/vm/flow_graph_compiler_mips.cc
===================================================================
--- runtime/vm/flow_graph_compiler_mips.cc	(revision 42479)
+++ runtime/vm/flow_graph_compiler_mips.cc	(working copy)
@@ -1395,6 +1395,8 @@
     bool needs_number_check,
     intptr_t token_pos) {
   __ TraceSimMsg("EqualityRegConstCompare");
+  ASSERT(!needs_number_check ||
+         (!obj.IsMint() && !obj.IsDouble() && !obj.IsBigint()));
   if (needs_number_check) {
     StubCode* stub_code = isolate()->stub_code();
     ASSERT(!obj.IsMint() && !obj.IsDouble() && !obj.IsBigint());
@@ -1416,13 +1418,27 @@
     }
     __ TraceSimMsg("EqualityRegConstCompare return");
     // Stub returns result in CMPRES1 (if it is 0, then reg and obj are
-    // equal) and always sets CMPRES2 to 0.
+    // equal).
     __ lw(reg, Address(SP, 1 * kWordSize));  // Restore 'reg'.
     __ addiu(SP, SP, Immediate(2 * kWordSize));  // Discard constant.
+    return Condition(CMPRES1, ZR, EQ);
   } else {
-    __ CompareObject(CMPRES1, CMPRES2, reg, obj);
+    Register obj_reg = CMPRES1;
+    int16_t imm = 0;
+    if (obj.IsSmi()) {

[zra, 2014/12/19 17:49:47]

Code like this (from here down to the LoadObject) is copied in a few places. Can
it be split out into a function? It's a little different each time, so I'm not
sure.

[regis, 2014/12/22 20:17:34]

There are 3 places with similar code. I moved the code to a new assembler method
LoadConditionOperand.

+      int32_t val = reinterpret_cast<int32_t>(obj.raw());
+      if (val == 0) {
+        obj_reg = ZR;
+      } else if (Condition::IsValidImm(val)) {
+        obj_reg = IMM;
+        imm = val;
+      }
+    }
+    if (obj_reg == CMPRES1) {
+      __ LoadObject(obj_reg, obj);
+    }
+    return Condition(reg, obj_reg, EQ, imm);
   }
-  return EQ;
 }
 
 
@@ -1458,15 +1474,14 @@
 #endif
     __ TraceSimMsg("EqualityRegRegCompare return");
     // Stub returns result in CMPRES1 (if it is 0, then left and right are
-    // equal) and always sets CMPRES2 to 0.
+    // equal).
     __ lw(right, Address(SP, 0 * kWordSize));
     __ lw(left, Address(SP, 1 * kWordSize));
     __ addiu(SP, SP, Immediate(2 * kWordSize));
+    return Condition(CMPRES1, ZR, EQ);
   } else {
-    __ slt(CMPRES1, left, right);
-    __ slt(CMPRES2, right, left);
+    return Condition(left, right, EQ);
   }
-  return EQ;
 }